Novel 3D Integration Method using SOI Substrates and Structures Produced Thereby

Abstract

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

1 - 6 . (canceled) 
     
     
         7 . A method of fabricating an enhanced 3D device stack comprising the steps of:
 fabricating silicon on insulator (SOI) circuits on a first SOI wafer with a buried oxide (BOX) layer;   providing a first set of middle of the line (MOL) interconnects for said SOI circuits;   patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer;   filling and planarizing said vias and said alignment marks with metal;   completing a first set of BEOL interconnects to connect said SOI circuits;   providing a first set of bonding pad level atop said first set of BEOL interconnects;   fabricating a second device wafer with a set of circuits, second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads;   flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other;   bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads;   removing the silicon substrate from said first SOI wafer by a grinding, polishing and etching or combinations thereof and stopping on said BOX layer and exposing said metal filled vias and alignment marks;   fabricating a third set of interconnects atop the BOX layer using said alignment marks as reference and connecting to the exposed ends of said vias; and   providing input output pads and solder connection means atop the top surface of said third set of interconnects to enable connections to a packaging substrate.   
     
     
         8 . A method according to  claim 7  wherein the metal used to fill said vias in said first device wafer comprises tungsten, molybdenum, ruthenium, nickel and cobalt and alloys thereof and mixtures thereof. 
     
     
         9 - 16 . (canceled)