Inventor · disambiguated record
Roy R. Yu
Also filed as: YU ROY · YU ROY R · Yu Roy Ronguing
16 granted patents·6 pending applications·394 citations·filing 1999–2023
91Inventor score
Top patents by PatentIndex Score
22 records- 0199US8129256B23D integrated circuit device fabrication with precisely controllable substrate removalFAROOQ MUKTA G·Filed 2008·Granted Mar 6, 2012·254 cites·18 claims
- 0297US8546188B2Bow-balanced 3D chip stackingLIU FEI·Filed 2010·Granted Oct 1, 2013·82 cites·24 claims
- 0386US8492869B23D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layerFAROOQ MUKTA G·Filed 2012·Granted Jul 23, 2013·5 cites·20 claims
- 0484US8298914B23D integrated circuit device fabrication using interface wafer as permanent carrierFAROOQ MUKTA G·Filed 2008·Granted Oct 30, 2012·7 cites·10 claims
- 0575US8664081B2Method for fabricating 3D integrated circuit device using interface wafer as permanent carrierFAROOQ MUKTA G·Filed 2012·Granted Mar 4, 2014·2 cites·20 claims
- 0673US6339527B1Thin film capacitor on ceramicIBM·Filed 1999·Granted Jan 15, 2002·41 cites·20 claims
- 0769US8399336B2Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layerFAROOQ MUKTA G·Filed 2008·Granted Mar 19, 2013·2 cites·20 claims
- 0864US8629553B23D integrated circuit device fabrication with precisely controllable substrate removalFAROOQ MUKTA G·Filed 2012·Granted Jan 14, 2014·1 cites·20 claims
- 0959US12456709B2Structures and processes for void-free hybrid bondingIBM·Filed 2022·Granted Oct 28, 2025·0 cites·5 claims
- 1058US12002758B2Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layerIBM·Filed 2021·Granted Jun 4, 2024·0 cites·20 claims
- 1158US11915966B2Backside power rail integrationIBM·Filed 2021·Granted Feb 27, 2024·0 cites·7 claims
- 1257US12136655B2Backside electrical contacts to buried power railsIBM·Filed 2021·Granted Nov 5, 2024·0 cites·16 claims
- 1357US12106969B2Substrate thinning for a backside power distribution networkIBM·Filed 2021·Granted Oct 1, 2024·0 cites·17 claims
- 1457US2017229392A1Novel 3D Integration Method Using SOI Substrates and Structures Produced TherebyIBM·Filed 2017·Application pending·0 cites
- 1556US2024332398A1High density metal-insulator-metal capacitorIBM·Filed 2023·Application pending·0 cites
- 1655US8962448B2Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrierFAROOQ MUKTA G·Filed 2012·Granted Feb 24, 2015·0 cites·20 claims
- 1754US2015270172A1Novel 3D Integration Method using SOI Substrates and Structures Produced TherebyIBM·Filed 2015·Application pending·0 cites
- 1853US8738167B23D integrated circuit device fabrication with precisely controllable substrate removalFAROOQ MUKTA G·Filed 2012·Granted May 27, 2014·0 cites·19 claims
- 1951US2023154784A1Bottom dielectric isolation integration with buried power railIBM·Filed 2021·Application pending·0 cites
- 2050US2023094466A1Nanosheet transistors with buried power railsIBM·Filed 2021·Application pending·0 cites
- 2146US9171742B2Alignment of integrated circuit chip stackIBM·Filed 2013·Granted Oct 27, 2015·0 cites·20 claims
- 2243US2017271207A9Novel 3D Integration Method Using SOI Substrates And Structures Produced TherebyPURUSHOTHAMAN SAMPATH·Filed 2013·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Roy R. Yu files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →