Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby

Abstract

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

1 - 16 . (canceled) 
     
     
         17 . An article of manufacture comprising at least two bonded device layers of which at least one first device layer comprises silicon on insulator (SOI) circuits disposed on a buried oxide (BOX) layer having a BOX surface and a first set of middle of the line (MOL) interconnects and a first set of back end of the line (BEOL) interconnects disposed thereon, said at least one first device layer further being flipped and bonded atop a second device layer located on its parent wafer and comprising a second set of circuits, a second set of middle of line interconnects and a second set of BEOL interconnects, and said at least one first device layer and said second device layer being interconnected together by means of metal filled vias located within said first set of MOL interconnects and said BOX layer of said at least one first device layer and connecting on one end to bonding pads associated with said second device layer and on the other end to metal features provided on a third set of BEOL interconnects located atop said BOX surface, where said third set of BEOL interconnects located atop said BOX surface is not directly in contact with said SOI circuits of said at least one first device layer, thus forming an enhanced 3D device stack. 
     
     
         18 . An article of manufacture according to  claim 17  further comprising input output terminals atop a third set of BEOL interconnects of said at least one first device layer to enable connection of the said enhanced 3D device stack to packaging substrates of an electronic system. 
     
     
         19 . An article of manufacture according to  claim 17  wherein said second set of circuits in said second device layer is one of SOI circuits and bulk silicon circuits. 
     
     
         20 . An article of manufacture according to  claim 17  wherein said metal filled vias are filled with a metal comprising tungsten, molybdenum, ruthenium, nickel, cobalt and copper and alloys thereof and mixtures thereof. 
     
     
         21 . An article of manufacture according to  claim 17  that incorporates lithographic fabrication of said third set of BEOL interconnects wherein some of said metal filled vias are used as alignment marks in said lithographic fabrication of said third set of BEOL interconnects on said first device layer. 
     
     
         22 . An article of manufacture according to  claim 17  wherein said metal filled vias range in height from about 0.25 micron to about 2 um enabling ease of patterning and filling with metal. 
     
     
         23 . An article of manufacture according to  claim 17  wherein said metal filled vias range in height from about 0.5 to about 1.0 micron enabling ease of patterning and filling with metal. 
     
     
         24 . A product made by the process of fabricating an enhanced 3D device stack comprising the steps of:
 fabricating silicon on insulator (SOI) circuits on a first SOI wafer with a buried oxide (BOX) layer;   providing a first set of middle of the line (MOL) interconnects for said SOI circuits;   patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer;   filling and planarizing said vias and said alignment marks with metal;   completing a first set of BEOL interconnects to connect said SOI circuits;   providing a first set of bonding pad level atop said first set of BEOL interconnects;   fabricating a second device wafer with a second set of circuits comprising a second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads;   flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other;   bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads;   removing the silicon substrate from said first SOI wafer by a grinding, polishing and etching or combinations thereof and stopping on said BOX layer and exposing said metal filled vias and alignment marks;   fabricating a third set of interconnects atop said BOX layer using said alignment marks as reference and connecting to the exposed ends of said vias; and   providing input output pads and solder connection means atop the top surface of said third set of interconnects to enable connections to a packaging substrate.   
     
     
         25 . A product according to  claim 24  wherein the metal used to fill said vias in said first device wafer comprises tungsten, molybdenum, ruthenium, nickel and cobalt and alloys thereof and mixtures thereof. 
     
     
         26 . A product according to  claim 24  including the process steps associated with the fabrication of the first SOI wafer, comprising said bonding, and providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer, and further providing additional interconnects atop said BOX layer. 
     
     
         27 . A product according to  claim 26  wherein said process of providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer is repeated using additional SOI wafers so as to enable the incorporation of more than two device layers in the 3D stack. 
     
     
         28 . A product according to  claim 24  wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits. 
     
     
         29 . A product according to  claim 24  wherein said vias range in height from about 0.25 micron to about 2 um enabling ease of patterning and filling with metal. 
     
     
         30 . A product according to  claim 25  including the process steps associated with the fabrication of the first SOI wafer, comprising said bonding, and further providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer, and further providing additional interconnects atop said BOX layer. 
     
     
         31 . A product according to  claim 25  wherein said process of providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer is repeated using additional SOI wafers so as to enable the incorporation of more than two device layers in the 3D stack. 
     
     
         32 . A product according to  claim 25  wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits. 
     
     
         33 . A product according to  claim 25  wherein said vias range in height from about 0.25 micron to about 2 um enabling ease of patterning and filling with metal. 
     
     
         34 . A product according to  claim 26  including the process steps associated with the fabrication of the first SOI wafer, comprising said bonding, and further providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer, and further providing additional interconnects atop said BOX layer. 
     
     
         35 . A product according to  claim 34  wherein said process of providing a silicon wafer body below said BOX layer and then removing said silicon wafer body below said BOX layer is repeated using additional SOI wafers so as to enable the incorporation of more than two device layers in the 3D stack. 
     
     
         36 . A product according to  claim 26  wherein said second set of circuits comprises one of SOI circuits and bulk silicon circuits.