Method for applying a final metal layer for wafer level packaging and associated device

Abstract

A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substitute having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt, cobalt alloys, palladium, and palladium alloys.

1 . A wafer level device comprising:
 a semiconductor wafer substrate having a backside and a laser marked metal layer on the back side; and   a protective metal layer over the laser marked metal layer wherein the protective metal layer is comprised of a metal selected from the group consisting of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt and cobalt alloys, palladium and palladium alloys.   
     
     
         2 . The device of  claim 1  wherein the protective metal layer has a thickness between about 10 Angstroms and about 40,000 Angstroms. 
     
     
         3 . The device of  claim 1  wherein the protective metal layer is made of titanium. 
     
     
         4 . The device of  claim 1  wherein the primary metal layer is one of copper and a copper alloy. 
     
     
         5 . The method of  claim 1  wherein the backside of the semiconductor device wafer substrate consists of only a single metal layer comprising a single metal or metal alloy that is susceptible to corrosion and a single corrosion resistant metal layer comprising a single metal or metal alloy overlying the single backside metal layer. 
     
     
         6 . A wafer level device comprising:
 a semiconductor wafer substrate having a backside and a metal layer on the back side; and   a protective metal layer over the backside metal layer wherein the protective metal layer is comprised of a metal selected from the group consisting of chromium, chromium alloys, cobalt and cobalt alloys, palladium and palladium alloys.   
     
     
         7 . The wafer level device of  claim 6 , further comprising an adhesion layer between the backside and the backside metal layer.