Inventor · disambiguated record
Anthony P. Curtis
Also filed as: CURTIS ANTHONY · CURTIS ANTHONY P · CURTIS ANTHONY PAUL
7 granted patents·3 pending applications·30 citations·filing 2005–2015
81Inventor score
Top patents by PatentIndex Score
10 records- 0188US8754524B2Wafer-level interconnect for high mechanical reliability applicationsCURTIS ANTHONY·Filed 2012·Granted Jun 17, 2014·6 cites·16 claims
- 0284US8143722B2Wafer-level interconnect for high mechanical reliability applicationsCURTIS ANTHONY·Filed 2007·Granted Mar 27, 2012·11 cites·8 claims
- 0380US9627254B2Method for building vertical pillar interconnectFLIPCHIP INT LLC·Filed 2013·Granted Apr 18, 2017·7 cites·31 claims
- 0460US9070747B2Electroplating using dielectric bridgesFLIPCHIP INT LLC·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 0559US8058163B2Enhanced reliability for semiconductor devices using dielectric encasementRECHE JOHN J H·Filed 2009·Granted Nov 15, 2011·4 cites·20 claims
- 0656US8980743B2Method for applying a final metal layer for wafer level packaging and associated deviceFLIPCHIP INT LLC·Filed 2013·Granted Mar 17, 2015·1 cites·14 claims
- 0738US2015270223A1Method for applying a final metal layer for wafer level packaging and associated deviceBURGESS GUY F·Filed 2014·Application pending·0 cites
- 0835US2009014869A1Semiconductor device package with bump overlying a polymer layerVRTIS JOAN K·Filed 2005·Application pending·0 cites
- 0934US2011003470A1Methods and structures for a vertical pillar interconnectFLIPCHIP INT LLC·Filed 2010·Application pending·0 cites
- 1027US9831201B2Methods for forming pillar bumps on semiconductor wafersBURGESS GUY F·Filed 2015·Granted Nov 28, 2017·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →