DRAM Cells and Methods of Forming Silicon Dioxide

Abstract

Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

I/we claim: 
     
         1 . A method of forming a transistor, comprising:
 forming a trench extending into monocrystalline silicon, the trench exposing multiple crystallographic planes of the monocrystalline silicon;   forming silicon dioxide along the multiple crystallographic planes along an interior surface of the trench utilizing a first treatment temperature of less than or equal to about 1000° C.;   annealing an interface between the silicon dioxide and the monocrystalline silicon utilizing a second treatment temperature which is at least about 1050° C.;   forming a transistor gate within the trench and spaced from the monocrystalline silicon by the silicon dioxide; and   forming a pair of source/drain regions within the monocrystalline silicon; with the source/drain regions being on opposing sides of the transistor gate from one another.   
     
     
         2 . The method of  claim 1  wherein the silicon dioxide is formed to have a thickness of from 45 Å to 75 Å. 
     
     
         3 . The method of  claim 1  wherein:
 the forming of the silicon dioxide comprises thermal growth utilizing radical oxidation and/or furnace oxidation; 
 the first treatment temperature is within a range of from about 700° C. to about 1000° C.; and 
 the second treatment temperature is within a range of from about 1050° C. to about 1200° C. 
 
     
     
         4 . A DRAM cell comprising a transistor formed by the method of  claim 1 . 
     
     
         5 . The DRAM cell of  claim 4  within an array having a time to 200 bit per die failure of at least about 400 milliseconds for charge retention. 
     
     
         6 . A DRAM cell comprising:
 a gate spaced from a silicon-containing channel region by silicon dioxide;   source/drain regions on opposing sides of the gate relative to one another;   a charge-storage device coupled to one of the source/drain regions;   wherein the silicon dioxide being formed utilizing the two stages of (1) growing silicon dioxide across a silicon-containing surface utilizing a first treatment temperature of less than or equal to about 1000° C., and (2) annealing an interface between the silicon dioxide and the silicon-containing surface utilizing a second treatment temperature which is at least about 1050° C.;   wherein the gate has a width of less than or equal to about 40 nanometers; and   wherein the DRAM cell is within an array having a time to 200 bit per die failure of at least about 400 milliseconds for charge retention.   
     
     
         7 . The DRAM cell of  claim 6  wherein the silicon dioxide has a thickness of from 45 Å to 75 Å. 
     
     
         8 . The DRAM cell of  claim 6  wherein the array is an array of substantially identical DRAM cells. 
     
     
         9 . The DRAM cell of  claim 6  wherein the silicon dioxide is within an opening that extends into a monocrystalline silicon base and wherein the silicon oxide extends across multiple planes of the monocrystalline silicon. 
     
     
         10 . A method of forming a transistor, comprising:
 forming a trench extending into monocrystalline silicon;   forming silicon dioxide along an interior surface of the trench utilizing a first treatment temperature of less than or equal to about 1000° C., the silicon dioxide having a thickness of from 45 Å to 75 Å;   annealing an interface between the silicon dioxide and the monocrystalline silicon utilizing a second treatment temperature which is at least about 1050° C.;   forming a transistor gate within the trench and spaced from the monocrystalline silicon by the silicon dioxide; and   forming a pair of source/drain regions within the monocrystalline silicon.   
     
     
         11 . The method of  claim 10  wherein the source/drain regions are on opposing sides of the transistor gate from one another. 
     
     
         12 . The method of  claim 10  wherein the annealing the interface utilizes a single thermal treatment. 
     
     
         13 . The method of  claim 12  wherein the single thermal treatment is performed in a reaction chamber having an ambient atmosphere consisting essentially of N 2 . 
     
     
         14 . The method of  claim 13  wherein the silicon dioxide is uncovered and fully exposed to the ambient atmosphere during the annealing. 
     
     
         15 . The method of  claim 10  wherein the silicon dioxide is thermally grown. 
     
     
         16 . The method of  claim 10 , further comprising cooling the interface to a temperature below the first treatment temperature prior to the annealing of the interface. 
     
     
         17 . The method of  claim 16  wherein the cooling of the interface comprises cooling the interface to a temperature of less than about 700° C. 
     
     
         18 . The method of  claim 10  wherein the first treatment temperature is at least about 700° C. and the second treatment temperature is from 1050° C. to about 1200° C. 
     
     
         19 . A transistor formed by the method of  claim 10 . 
     
     
         20 . A DRAM cell comprising a transistor formed by the method of  claim 10 .