Field effect transistor and method of fabricating the same

Abstract

Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

What is claimed is: 
     
         1 . A method of fabricating a field effect transistor, comprising:
 patterning a substrate to form an active fin;   forming a gate insulating layer to cover the active fin;   forming a sacrificial gate pattern on the gate insulating layer to cross the active fin;   forming a gate spacer on a sidewall of the sacrificial gate pattern;   forming a source electrode at on side of the sacrificial gate pattern;   forming a drain electrode at another side of the sacrificial gate pattern;   forming silicide patterns on the source and drain electrodes, respectively; and   replacing the sacrificial gate pattern with a gate pattern.   
     
     
         2 . The method of  claim 1 , wherein the gate insulating layer is formed of at least one high-k dielectric, and the method further comprises performing a thermal treatment after forming the gate insulating layer and before forming of the silicide pattern. 
     
     
         3 . The method of  claim 2 , wherein the silicide pattern is formed of at least one of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide. 
     
     
         4 . The method of  claim 2 , wherein the gate insulating layer remains after replacing the sacrificial gate pattern with the gate pattern, thereby being at least a portion of a gate dielectric of the field effect transistor. 
     
     
         5 . The method of  claim 1 , wherein the gate spacer has a dielectric constant smaller than the gate insulating layer. 
     
     
         6 . The method of  claim 1 , wherein the active fin comprises a channel region below the sacrificial gate pattern and source and drain regions at both sides of the channel region, and wherein forming the sacrificial gate pattern further comprises etching the gate insulating layer to expose the source and drain regions of the active fin. 
     
     
         7 . The method of  claim 6 , wherein forming the sacrificial gate pattern further comprises etching the exposed source and drain regions to transform the source and drain regions of the active fin into a tapered structure whose width decreases upward. 
     
     
         8 . The method of  claim 1 , wherein forming the active fin comprises forming a channel region below the sacrificial gate pattern and the source and drain regions, and wherein forming the gate spacer comprises exposing the source and drain regions of the active fin. 
     
     
         9 . The method of  claim 1 , wherein forming the active fin comprises:
 patterning the substrate to form device isolation trenches;   forming a device isolation layer to fill the device isolation trenches; and   recessing a top surface of the device isolation layer to form device isolation patterns having top surfaces lower than that of the substrate.   
     
     
         10 . The method of  claim 1 , wherein the gate insulating layer is formed to have a single- or multi-layered structure. 
     
     
         11 . The method of  claim 1 , wherein the substrate comprises an NMOS region and a PMOS region, and wherein forming of the source/drain electrodes comprises:
 forming an epitaxial layer having a tensile strain property in the NMOS region; and   forming an epitaxial layer having a compressive strain property in the PMOS region.   
     
     
         12 . The method of  claim 1 , wherein the replacing of the sacrificial gate pattern with the gate pattern comprises:
 removing the sacrificial gate pattern to expose the gate insulating layer; and   forming a gate layer on the exposed gate insulating layer,   wherein removing the sacrificial gate pattern is performed using an etch recipe having an etch selectivity with respect to the gate insulating layer and the gate spacer.   
     
     
         13 . The method of  claim 12 , wherein forming the gate layer comprises:
 forming a work-function controlling layer on the exposed gate insulating layer; and   forming a metal layer on the work-function controlling layer.   
     
     
         14 . The method of  claim 1 , wherein the sacrificial gate pattern comprises a lower sacrificial pattern conformally covering the gate insulating layer and an upper sacrificial pattern formed on the lower sacrificial pattern, and wherein replacing of sacrificial gate pattern with the gate pattern comprises:
 selectively removing the upper sacrificial pattern using the lower sacrificial pattern as an etch stop layer; and   selectively removing the lower sacrificial pattern using an etch recipe having etch selectivity with respect to the gate insulating layer.