Method of fabricating semiconductor device

Abstract

A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures.

1 .- 20 . (canceled) 
     
     
         21 . A method of forming a semiconductor device, the method comprising:
 forming device isolation patterns in a substrate to define active portions therein, the active portions being spaced apart from each other in a first direction and extending in a second direction that is substantially perpendicular to the first direction;   forming a plurality of gate patterns on the substrate, each of the plurality of gate patterns extending in the first direction and spaced apart from each other in the second direction to provide spaces between ones of the plurality of gate patterns;   recessing upper surface of the device isolation patterns which are exposed by the plurality of gate patterns; and   forming air gaps between the plurality of gate patterns.   
     
     
         22 . The method as claimed in  claim 21 , wherein each of the air gaps includes an undercut formed under adjacent gate patterns, such that a maximum width of the air gaps between the adjacent gate patterns is greater than a distance between the adjacent gate patterns. 
     
     
         23 . The method as claimed in  claim 21 , wherein a lowermost level of the air gaps in the active portion is coplanar with the lowermost level of the gate patterns in the active portions. 
     
     
         24 . The method as claimed in  claim 21 , wherein recessing upper surface of the device isolation patterns comprises isotropically etching the device isolation patterns. 
     
     
         25 . The method as claimed in  claim 21 , wherein recessing upper surface of the device isolation patterns comprises partially etching the device isolation patterns by a wet etch process. 
     
     
         26 . The method as claimed in  claim 21 , wherein a lowermost level of the air gaps in the active portion is lower than a lowermost level of the air gaps on the device isolation patterns. 
     
     
         27 . The method as claimed in  claim 21 , wherein forming air gaps comprises forming an interlayer insulation layer over the plurality gate patterns. 
     
     
         28 . The method as claimed in  claim 27 , wherein an uppermost level of lower surface of the interlayer insulating layer is higher than the uppermost level of gate patterns. 
     
     
         29 . The method as claimed in  claim 21 , wherein a difference between a vertical height of the gate patterns and a vertical height of the air gaps in the active portion is smaller than a difference between a vertical height of the gate patterns and a vertical height of the air gaps on the device isolation patterns. 
     
     
         30 . The method as claimed in  claim 29 , wherein the vertical height of the gate patterns in the active portion is greater than the vertical height of the gate patterns on the device isolation patterns.