Semiconductor package

Abstract

A semiconductor package includes a trace molding compound layer and a chip molding compound layer. The trace molding compound layer has a first surface and a second surface, wherein the trace molding compound layer encapsulates a plurality of traces and studs between the first and second surface. The chip molding compound layer has a first surface and a second surface, wherein the chip molding compound layer encapsulates a semiconductor chip between the first and second surface of the chip molding compound layer. The chip molding compound layer is disposed on the trace molding compound layer, the second surface of the chip molding compound layer adheres to the first surface of the trace molding compound layer, and the chip molding compound layer and the trace molding compound layer comprise substantially the same molding compound material.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a trace molding compound layer having a first surface and a second surface opposite the first surface, wherein the trace molding compound layer encapsulates a plurality of traces and studs between the first and second surface of the trace molding compound layer, each of the plurality of traces having a trace upper surface and a trace lower surface opposite the trace upper surface, each of the plurality of studs having a stud upper surface and a stud lower surface opposite the stud upper surface, the trace upper surface is exposed on the first surface of the trace molding compound layer, the stud lower surface is exposed on the second surface of the trace molding compound layer and the stud upper surface adjoins the trace lower surface within the trace molding compound layer; and   a chip molding compound layer having a first surface and a second surface opposite the first surface, wherein the chip molding compound layer encapsulates at least one semiconductor chip between the first and second surface of the chip molding compound layer;—   wherein the chip molding compound layer is disposed on the trace molding compound layer, the second surface of the chip molding compound layer adheres to the first surface of the trace molding compound layer and the trace upper surface, and the chip molding compound layer and the trace molding compound layer comprise substantially the same molding compound material.   
     
     
         2 . The semiconductor package according to  claim 1 , further comprising:
 a plurality of trace pads, wherein each trace pad corresponds to one trace and is disposed on the trace upper surface.   
     
     
         3 . The semiconductor package according to  claim 2 , wherein the studs are disposed a distance away from the corresponding trace pads. 
     
     
         4 . The semiconductor package according to  claim 2 , wherein the studs are disposed opposite to the corresponding trace pads. 
     
     
         5 . The semiconductor package according to  claim 2 , further comprising:
 a plurality of trace supporting studs, each having a trace supporting stud upper surface and a trace supporting the stud lower surface opposite the trace supporting stud upper surface; wherein each trace supporting stud corresponds to one trace pad and is disposed on the trace lower surface opposite the corresponding trace pad;   wherein the trace molding compound layer further encapsulates the trace supporting studs, the trace supporting stud upper surface adjoins the trace lower surface and extends to the second surface of the trace molding compound layer.   
     
     
         6 . The semiconductor package according to  claim 5 , further comprising:
 an insulation layer disposed on the second surface of the trace molding compound layer and the trace supporting the stud lower surfaces, and exposing the trace supporting the stud lower surfaces through a plurality of openings in the insulation layer.   
     
     
         7 . The semiconductor package according to  claim 2 , further comprising:
 a chip base, having a chip base upper surface and a chip base lower surface opposite the chip base upper surface;   wherein the trace molding compound layer further encapsulates the chip base, the chip base extends from the first surface of the trace molding compound layer towards the second surface of the trace molding compound layer, the semiconductor chip is disposed on the chip base.   
     
     
         8 . The semiconductor package according to  claim 7 , further comprising:
 a plurality of chip base supporting studs, having a chip base supporting stud upper surface and a chip base supporting stud lower surface, each chip base supporting stud is disposed on the chip base lower surface;   wherein the trace molding compound layer further encapsulates the chip base supporting studs, the chip base supporting stud upper surface adjoins the chip base lower surface and extends to the second surface of the trace molding compound layer.   
     
     
         9 . The semiconductor package according to  claim 8 , further comprising:
 an insulation layer disposed on the second surface of the trace molding compound layer and the chip base supporting stud lower surfaces, and exposing the chip base supporting lower surfaces through a plurality of openings in the insulation layer.   
     
     
         10 . The semiconductor package according to  claim 2 , further comprising:
 an insulation layer disposed between the lower surface of the chip molding compound layer and the upper surface of the trace molding compound layer, wherein the insulation layer has a plurality of openings corresponding to and exposing the trace pads.   
     
     
         11 . The semiconductor package according to  claim 7 , further comprising:
 an insulation layer disposed between the lower surface of the chip molding compound layer and the upper surface of the trace molding compound layer, wherein the insulation layer has a plurality of openings corresponding to and exposing the trace pads and the chip base.   
     
     
         12 . The semiconductor package according to  claim 2 , wherein the trace pads are arranged surrounding the semiconductor chip and the studs are arranged below the semiconductor chip, the trace pads and the lateral side of the trace molding compound layer are separated by a first distance, the studs and the lateral side of the trace molding compound layer are separated by a second distance, and the first distance differs with the second distance. 
     
     
         13 . The semiconductor package according to  claim 2 , wherein the studs are arranged along a first border surrounding the semiconductor chip and the trace pads are arranged along a second border surrounding the semiconductor chip;
 wherein the distance of the first border to the lateral side of the trace molding compound layer differs from the distance of the second border to the lateral side of the trace molding compound layer.   
     
     
         14 . The semiconductor package according to  claim 2 , wherein the studs comprise a plurality of first studs and a plurality of second studs, the first studs are arranged surrounding the semiconductor chip and the second studs are arranged below the semiconductor chip. 
     
     
         15 . The semiconductor package according to  claim 7 , wherein the trace pads are arranged surrounding the semiconductor chip and the studs are arranged below the semiconductor chip, the trace pads and the lateral side of the trace molding compound layer are separated by a first distance, the studs and the lateral side are separated by a second distance, and the first distance differs with the second distance. 
     
     
         16 . The semiconductor package according to  claim 7 , wherein the studs are arranged along a first border surrounding the chip base and the trace pads are arranged along a second border surrounding the chip base;
 wherein the distance of the first border to the lateral side of the trace molding compound layer differs from the distance of the second border to the lateral side of the trace molding compound layer.   
     
     
         17 . The semiconductor package according to  claim 7 , wherein the studs comprise a plurality of first studs and a plurality of second studs, the first studs are arranged surrounding the semiconductor chip and the second studs are arranged below the semiconductor chip. 
     
     
         18 . A semiconductor package, comprising:
 a trace molding compound layer having a first surface and a second surface opposite the first surface, wherein the trace molding compound layer encapsulates a plurality of traces and studs between the first and second surface of the trace molding compound layer to form part of or whole of a trace substrate, and the plurality of traces and studs connect the first surface of the trace molding compound layer to the second surface of the trace molding compound layer; and   a chip molding compound layer having a first surface and a second surface opposite the first surface, wherein the chip molding compound layer encapsulates at least one semiconductor chip between the first and second surface of the chip molding compound layer to form a chip substrate;   wherein the chip substrate is disposed on the trace substrate, the second surface of the chip molding compound layer adheres to the first surface of the trace molding compound layer, and the chip molding compound layer and the trace molding compound layer comprise substantially the same molding compound material.