Implementation of load acquire/store release instructions using load/store operation with dmb operation

Abstract

A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.

What is claimed is: 
     
         1 . A processor that executes computer-executable instructions to perform operations, the instructions comprising:
 a load with acquire instruction that performs memory operation ordering, wherein the load with acquire instruction comprises a load operation followed by a data memory barrier operation.   
     
     
         2 . The processor of  claim 1 , wherein the processor is an ARMv8 processor. 
     
     
         3 . The processor of  claim 1 , wherein the data memory barrier operation orders memory operations comprising a first set of memory operations occurring before the barrier operation, and a second set of memory operations occurring after the barrier operation. 
     
     
         4 . The processor of  claim 1 , wherein the load operation specifies an address for accessing a first data from the memory. 
     
     
         5 . The processor of  claim 1 , wherein the load with acquire instruction comprises at least one of a plurality of types of load with acquire instructions. 
     
     
         6 . The processor of  claim 1 , wherein the data memory barrier operation replaces a set of load acquire semantics for memory operation ordering. 
     
     
         7 . A method for executing instructions in a processor, comprising:
 executing a load with acquire instruction for performing memory operation ordering, wherein the executing the load with acquire instruction comprises executing a load operation followed by a data memory barrier operation.   
     
     
         8 . The method of  claim 7 , further comprising executing the instructions on an ARMv8 processor. 
     
     
         9 . The method of  claim 7 , further comprising executing a plurality of types of load with acquire instructions. 
     
     
         10 . The method of  claim 7 , wherein executing the data memory barrier operation replaces a set of load acquire semantics for memory operation ordering. 
     
     
         11 . The method of  claim 7 , wherein the load operation specifies an address for accessing a first data from the memory. 
     
     
         12 . The method of  claim 7 , wherein the data memory barrier operation orders memory operations comprising a first set of memory operations occurring before the barrier operation, and a second set of memory operations occurring after the barrier operation. 
     
     
         13 . A processor that executes computer-executable instructions to perform operations, the instructions comprising:
 a store with release instruction that performs memory operation ordering, wherein the store with release instruction comprise a first data memory barrier operation followed by a store operation followed by a second data memory barrier operation.   
     
     
         14 . The processor of  claim 13 , wherein the processor is an ARMv8 processor. 
     
     
         15 . The processor of  claim 13 , wherein the first and second data memory barrier operations order memory operations comprising a first set of memory operations occurring before the barrier operations, and a second set of memory operations occurring after the barrier operations. 
     
     
         16 . The processor of  claim 13 , wherein the store operation specifies an address for writing a first data to memory. 
     
     
         17 . The processor of  claim 13 , wherein the instructions further comprise a plurality of types of store with release instructions. 
     
     
         18 . The processor of  claim 13 , wherein the second data memory barrier operation ensures that a following load with acquire instruction is observed in a program order. 
     
     
         19 . The processor of  claim 13 , wherein the data memory barrier operations replaces a set of store release semantics for memory operation ordering. 
     
     
         20 . A method for executing instructions in a processor, comprising:
 executing a store with release instruction for performing memory operation ordering, wherein executing the store with release instruction comprises executing a first data memory barrier operation followed by executing a store operation followed by executing a second data memory barrier operation.   
     
     
         21 . The method of  claim 20 , further comprising executing the store with release instruction on an ARMv8 processor. 
     
     
         22 . The method of  claim 20 , further comprising executing a plurality of types of store with release instructions. 
     
     
         23 . The method of  claim 20 , wherein executing the data memory barrier operations replaces a set of store release semantics for memory operation ordering. 
     
     
         24 . The method of  claim 20 , wherein executing the first and second data memory barrier operations order memory operations comprising a first set of memory accesses occurring before the barrier operations, and a second set of memory accesses occurring after the barrier operations. 
     
     
         25 . The method of  claim 20 , wherein executing the store operations specifies an address for writing a first data to memory. 
     
     
         26 . The method of  claim 20 , wherein the executing the second data memory barrier operation before executing a load with acquire instruction ensures the instructions are observed in a program order.