Inventor · disambiguated record
Matthew William Ashcraft
Also filed as: ASHCRAFT MATTHEW · ASHCRAFT MATTHEW W · ASHCRAFT MATTHEW WILLIAM
24 granted patents·4 pending applications·332 citations·filing 2006–2024
96Inventor score
Files withORACLE AMERICA INC9ASHCRAFT MATTHEW W4GOOGLE LLC4AMPERE COMPUTING LLC3APPLIED MICRO CIRCUITS CORP2
Top patents by PatentIndex Score
28 records- 0196US10348281B1Clock control based on voltage associated with a microprocessorAMPERE COMPUTING LLC·Filed 2016·Granted Jul 9, 2019·20 cites·15 claims
- 0295US8850121B1Outstanding load miss buffer with shared entriesASHCRAFT MATTHEW W·Filed 2011·Granted Sep 30, 2014·37 cites·20 claims
- 0394US7788473B1Prediction of data values read from memory by a microprocessor using the storage destination of a load operationORACLE AMERICA INC·Filed 2006·Granted Aug 31, 2010·47 cites·21 claims
- 0493US11314674B2Direct memory access architecture with multi-level multi-stridingGOOGLE LLC·Filed 2020·Granted Apr 26, 2022·4 cites·18 claims
- 0592US8037285B1Trace unitORACLE AMERICA INC·Filed 2007·Granted Oct 11, 2011·36 cites·2 claims
- 0691US11762793B2Direct memory access architecture with multi-level multi-stridingGOOGLE LLC·Filed 2022·Granted Sep 19, 2023·2 cites·20 claims
- 0791US7856548B1Prediction of data values read from memory by a microprocessor using a dynamic confidence thresholdORACLE AMERICA INC·Filed 2006·Granted Dec 21, 2010·30 cites·28 claims
- 0890US7941607B1Method and system for promoting traces in an instruction processing circuitORACLE AMERICA INC·Filed 2007·Granted May 10, 2011·17 cites·21 claims
- 0990US7814298B1Promoting and appending traces in an instruction processing circuit based upon a bias valueORACLE AMERICA INC·Filed 2007·Granted Oct 12, 2010·22 cites·15 claims
- 1089US8499293B1Symbolic renaming optimization of a traceASHCRAFT MATTHEW WILLIAM·Filed 2007·Granted Jul 30, 2013·33 cites·8 claims
- 1188US8793435B1Load miss result buffer with shared data linesASHCRAFT MATTHEW W·Filed 2011·Granted Jul 29, 2014·13 cites·26 claims
- 1287US8032710B1System and method for ensuring coherency in trace executionORACLE AMERICA INC·Filed 2007·Granted Oct 4, 2011·18 cites·42 claims
- 1386US8806135B1Load store unit with load miss result bufferASHCRAFT MATTHEW W·Filed 2011·Granted Aug 12, 2014·10 cites·23 claims
- 1486US7849292B1Flag optimization of a traceORACLE AMERICA INC·Filed 2007·Granted Dec 7, 2010·17 cites·13 claims
- 1582US9280479B1Multi-level store merging in a cache and memory hierarchyKRUCKEMYER DAVID A·Filed 2012·Granted Mar 8, 2016·8 cites·24 claims
- 1677US7937564B1Emit vector optimization of a traceORACLE AMERICA INC·Filed 2007·Granted May 3, 2011·9 cites·6 claims
- 1775US12287745B2Direct memory access architecture with multi-level multi-stridingGOOGLE LLC·Filed 2023·Granted Apr 29, 2025·0 cites·20 claims
- 1870US7783863B1Graceful degradation in a trace-based processorORACLE AMERICA INC·Filed 2007·Granted Aug 24, 2010·5 cites·18 claims
- 1969US9880849B2Allocation of load instruction(s) to a queue buffer in a processor system based on prediction of an instruction pipeline hazardAPPLIED MICRO CIRCUITS CORP·Filed 2013·Granted Jan 30, 2018·2 cites·22 claims
- 2068US8949581B1Threshold controlled limited out of order load executionASHCRAFT MATTHEW W·Filed 2011·Granted Feb 3, 2015·2 cites·40 claims
- 2160US11513798B1Implementation of load acquire/store release instructions using load/store operation with DMB operationAMPERE COMPUTING LLC·Filed 2019·Granted Nov 29, 2022·0 cites·24 claims
- 2259US2025117647A1Dynamic Exponent Bias Method for Neural Network TrainingSAMBANOVA SYSTEMS INC·Filed 2023·Application pending·0 cites
- 2355US12164917B1Transposing at-speed in a vector-matrix acceleratorGOOGLE LLC·Filed 2023·Granted Dec 10, 2024·0 cites·20 claims
- 2453US2025208839A1Compiler for Mixed Precision in a Computational GraphSAMBANOVA SYSTEMS INC·Filed 2024·Application pending·0 cites
- 2552US2015317158A1Implementation of load acquire/store release instructions using load/store operation with dmb operationAPPLIED MICRO CIRCUITS CORP·Filed 2014·Application pending·0 cites
- 2649US11744748B2Dryness layer laminate for absorbent articlesATTENDS HEALTHCARE PRODUCTS INC·Filed 2019·Granted Sep 5, 2023·0 cites·15 claims
- 2749US2022265488A1Absorbent laminate including a spunlace nonwoven layer, absorbent cores with such laminates, and absorbent articles with such absorbent coresATTENDS HEALTHCARE PRODUCTS INC·Filed 2020·Application pending·0 cites
- 2847US11093401B2Hazard prediction for a group of memory access instructions using a buffer associated with branch predictionAMPERE COMPUTING LLC·Filed 2014·Granted Aug 17, 2021·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →