Vertical floating gate nand with offset dual control gates

Abstract

A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.

What is claimed is: 
     
         1 . A method of making a monolithic three dimensional NAND string, comprising:
 providing a stack of alternating insulating layers and control gate films over a major surface of a substrate, each of the control gate films comprising: a middle layer located between a first control gate layer and a second control gate layer, the middle layer comprising a different material from the first and second control gate layers and from the insulating layers;   forming a front side opening in the stack; and   forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.   
     
     
         2 . The method of  claim 1 , further comprising removing a portion of the middle layer through the front side opening in the stack thereby forming a plurality of recesses, wherein each of the plurality of recesses is located in each respective control gate film between the first and second control gate layers. 
     
     
         3 . The method of  claim 2 , wherein forming the blocking dielectric comprises forming the blocking dielectric layer in the recesses and in the front side opening. 
     
     
         4 . The method of  claim 3 , wherein:
 the blocking dielectric is formed on an exposed edge surface of the middle layer in each of the plurality of recesses, on exposed major surfaces of the first and second control gate layers in each of the plurality of recesses, and on exposed edge surfaces of the first and second control gate layers in the front side opening;   the edge surface of the middle layer and the edge surfaces of the first and second control gate layers extend substantially perpendicular to the major surface of the substrate; and   the major surfaces of the first and second control gate layers extend substantially parallel to the major surface of the substrate.   
     
     
         5 . The method of  claim 4 , wherein forming the at least one charge storage region comprises:
 depositing a charge storage layer over the blocking dielectric;   removing a portion of the charge storage layer from the front side opening to expose the blocking dielectric located in the front side opening on the edge surfaces of the first and second control gate layers, to leave a plurality of the charge storage regions in a respective plurality of recesses.   
     
     
         6 . The method of  claim 5 , wherein:
 the plurality of charge storage regions comprise a plurality of floating gates;   forming the tunnel dielectric comprises depositing the tunnel dielectric on the blocking dielectric and on exposed portions of the plurality of charge storage regions in the front side opening; and   forming the semiconductor channel comprises depositing the semiconductor channel on the tunnel dielectric in the front side opening.   
     
     
         7 . The method of  claim 1 , wherein the middle layer comprises an electrically conductive middle layer which electrically contacts the first and second control gate layers in each control gate film. 
     
     
         8 . The method of  claim 1 , wherein the middle layer comprises a sacrificial middle layer. 
     
     
         9 . The method of  claim 8 , wherein the sacrificial middle layer comprises silicon nitride and the insulating layers comprise silicon oxide. 
     
     
         10 . The method of  claim 8 , further comprising:
 removing at least a portion of the sacrificial middle layer through the front side opening in the stack thereby forming a recess between the first and second control gate layers; and   forming an electrically conductive middle layer in the recess through the front side opening such that the electrically conducting middle layer electrically contacts the first and second control gate layers in each control gate film.   
     
     
         11 . The method of  claim 10 , wherein the electrically conductive middle layer comprises tungsten. 
     
     
         12 . The method of  claim 8 , further comprising:
 forming a back side opening in the stack;   removing at least a portion of the sacrificial middle layer through the back side opening in the stack thereby forming a recess between the first and second control gate layers; and   forming an electrically conductive middle layer in the recess through the back side opening such that the electrically conducting middle layer electrically contacts the first and second control gate layers in each control gate film.   
     
     
         13 . The method of  claim 12 , wherein the electrically conductive layer comprises tungsten. 
     
     
         14 . The method of  claim 1 , wherein the middle layer comprises an insulating middle layer, and further comprising:
 forming a back side opening in the stack;   removing a portion of the insulating middle layer through the back side opening in the stack thereby forming a recess between the first and second control gate layers; and   forming an electrically conductive connection layer in the recess through the back side opening such that the electrically conducting connection layer electrically contacts the first and second control gate layers in each control gate film and such that the electrically conductive connection layer is separated from the front side opening by a remaining portion of the insulating middle layer.   
     
     
         15 . The method of  claim 14 , wherein the insulating middle layer comprises silicon nitride and the insulating layers comprise silicon oxide. 
     
     
         16 . The method of  claim 1 , wherein:
 the semiconductor channel has a pillar shape; and   the entire semiconductor channel extends substantially perpendicular to the major surface of the substrate.   
     
     
         17 . The method of  claim 1 , wherein the semiconductor channel has a “U” shape with a horizontal portion substantially parallel to the major surface of the substrate and two wing portions substantially perpendicular to the major surface of the substrate. 
     
     
         18 . A monolithic three dimensional NAND string, comprising:
 a stack of alternating insulating layers and control gate films over a major surface of a substrate, each of the control gate films comprising: an insulating middle layer located between a first control gate layer and a second control gate layer, the insulating middle layer comprising a different material from the first and second control gate layers and from the insulating layers;   a semiconductor channel, wherein at least one end of the semiconductor channel extends through the stack substantially perpendicular to the major surface of the substrate;   a first charge storage region and a first portion of a blocking dielectric located in a recess between the first and the second control gate layers of a first control gate film in a first device level, wherein the first portion of the blocking dielectric is located between the first charge storage region and the insulating middle layer of the first control gate film;   a first electrically conductive connection layer which contacts the first and second control gate layers in the first control gate film, wherein the first electrically conductive connection layer is separated from the first charge storage region by the insulating middle layer of the first control gate film;   a second charge storage region and a second portion of the blocking dielectric located in a recess between the first and the second control gate layers of a second control gate film in a second device level, wherein the second portion of the blocking dielectric is located between the second charge storage region and the insulating middle layer of the second control gate film;   a second electrically conductive connection layer which contacts the first and second control gate layers in the second control gate film, wherein the second electrically conductive connection layer is separated from the second charge storage region by the insulating middle layer of the second control gate film; and   a tunnel dielectric located between the semiconductor channel and the first and second charge storage regions.   
     
     
         19 . The monolithic three dimensional NAND string of  claim 18 , wherein:
 the tunnel dielectric has a straight sidewall;   the first and the second portions of the blocking dielectric each have a clam shape; and   the first and the second charge storage regions comprise respective first and second floating gates which are located in an opening in respective clam shaped first and second portions of the blocking dielectric.   
     
     
         20 . The monolithic three dimensional NAND string of  claim 18 , wherein:
 the semiconductor channel has a pillar shape;   the entire semiconductor channel extends substantially perpendicular to the major surface of the substrate;   a first select gate is located adjacent to a first end of the semiconductor channel;   a second select gate is located adjacent to a second end of the semiconductor channel;   a first electrode which contacts the first end of the semiconductor channel; and   a second electrode which contacts the second end of the semiconductor channel.   
     
     
         21 . The monolithic three dimensional NAND string of  claim 18 , wherein:
 the semiconductor channel has a “U” shape with a horizontal portion substantially parallel to the major surface of the substrate and first and second wing portions substantially perpendicular to the major surface of the substrate;   a first select gate is located adjacent to the first wing portion;   a second select gate is located adjacent to the second wing portion;   a first electrode which contacts the first wing portion; and   a second electrode which contacts the second wing portion.   
     
     
         22 . The monolithic three dimensional NAND string of  claim 18 , wherein the insulating middle layer comprises silicon nitride and the insulating layers comprise silicon oxide.