Gallium nitride field effect transistor with buried field plate protected lateral channel

Abstract

A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.

What is claimed is: 
     
         1 . A lateral-drift GaN field-effect transistor (FET), comprising:
 a substrate;   a first GaN layer coupled to the substrate, wherein the first GaN layer has a first conductivity type;   a second GaN layer coupled to the first GaN layer, wherein the second GaN layer has a second conductivity type and comprises a void exposing a portion of the first GaN layer;   a third GaN layer coupled to the second GaN layer and to the exposed portion of the first GaN layer, wherein the third GaN layer has a third conductivity type and comprises a void exposing a portion of the second GaN layer;   a source structure coupled to the third GaN layer, wherein a first portion of the third GaN layer is disposed between the source structure and the second GaN layer;   a drain structure coupled to the third GaN layer; and   a gate structure coupled to the third GaN layer, wherein a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.   
     
     
         2 . The FET of  claim 1 , further comprising a contact coupled to the exposed portion of the second GaN layer. 
     
     
         3 . The FET of  claim 1 , wherein the second GaN layer comprises a plurality of sections that are progressively thinner as a distance from the second GaN layer to the gate structure increases. 
     
     
         4 . The FET of  claim 1 , wherein the gate structure comprises metal. 
     
     
         5 . The FET of  claim 1 , wherein the gate structure comprises GaN of the second conductivity type. 
     
     
         6 . The FET of  claim 1 , wherein the first portion of the third GaN layer is thinner than a second portion of the third GaN layer. 
     
     
         7 . The FET of  claim 1 , wherein the third GaN layer comprises n-type GaN. 
     
     
         8 . The FET of  claim 1 , wherein the second GaN layer comprises p-type GaN. 
     
     
         9 . The FET of  claim 1 , wherein at least one of the source structure, the drain structure, and the gate structure comprises a metal. 
     
     
         10 . The FET of  claim 1 , wherein at least one of the source structure, the drain structure, and the gate structure comprises a metal and a semiconductor material. 
     
     
         11 . The FET of  claim 1 , wherein a portion of the second GaN layer comprises a field plate structure. 
     
     
         12 . The FET of  claim 1 , wherein the drain structure does not overlap the second GaN layer. 
     
     
         13 . The FET of  claim 1 , wherein the second GaN layer extends from the gate structure toward the drain structure by at least 1 μm. 
     
     
         14 . A vertical-drift GaN field-effect transistor (FET), comprising:
 a substrate;   a first GaN layer coupled to the substrate, wherein the first GaN layer has a first conductivity type;   a second GaN layer coupled to the first GaN layer, wherein the second GaN layer has a second conductivity type and comprises a void exposing a portion of the first GaN layer;   a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer, wherein the third GaN layer has a third conductivity type and comprises a void exposing a portion of the second GaN layer;   a source structure coupled to the third GaN layer, wherein a first portion of the third GaN layer is disposed between the source structure and the second GaN layer;   a drain structure coupled to the substrate; and   a gate structure coupled to the third GaN layer, wherein a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.   
     
     
         15 . The FET of  claim 14 , wherein the second GaN layer comprises a plurality of sections that are progressively thinner as a distance from the second GaN layer to the gate structure increases. 
     
     
         16 . The FET of  claim 14 , wherein the first portion of the third GaN layer is thinner than the second portion of the third GaN layer. 
     
     
         17 . The FET of  claim 14 , wherein a portion of the second GaN layer comprises a field plate structure. 
     
     
         18 . The FET of  claim 14 , further comprising a contact structure coupled to the second GaN-based layer. 
     
     
         19 . The FET of  claim 14 , wherein the drain structure does not overlap the second GaN layer. 
     
     
         20 . The FET of  claim 14 , wherein the second GaN layer extends from the gate structure toward the drain structure by at least 1 μm.