Finfet semiconductor devices with improved source/drain resistance

Abstract

A FinFET device includes a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. A first layer of insulating material is positioned above a bottom surface of each of the plurality of spaced-apart trenches and an etch stop layer is positioned above an upper surface of the first layer of insulating material in each of the plurality of spaced-apart trenches. A metal silicide region is positioned on at least all sidewall surfaces of the fin that extend above the upper surface of the etch stop layer.

What is claimed: 
     
         1 . A FinFET device, comprising:
 a plurality of spaced-apart trenches in a semiconducting substrate, said plurality of spaced-apart trenches at least partially defining a fin for said FinFET device, wherein said fin comprises a first semiconductor material;   a first layer of insulating material positioned above a bottom surface of each of said plurality of spaced-apart trenches;   an etch stop layer positioned above an upper surface of said first layer of insulating material in each of said plurality of spaced-apart trenches; and   a metal silicide region positioned on at least all sidewall surfaces of said fin that extend above an upper surface of said etch stop layer.   
     
     
         2 . The FinFET device of  claim 1 , further comprising a gate structure positioned on and around said fin, wherein said gate structure extends across at least a portion of each of said plurality of spaced-apart trenches. 
     
     
         3 . The FinFET device of  claim 2 , wherein said gate structure comprises a gate insulation layer comprising a high-k dielectric material and a work-function adjusting metal layer positioned above said gate insulation layer. 
     
     
         4 . The FinFET device of  claim 2 , further comprising a second layer of insulating material positioned between a portion of said etch stop layer positioned in each of said plurality of spaced-apart trenches and a sidewall spacer positioned adjacent to sidewalls of said gate structure. 
     
     
         5 . The FinFET device of  claim 4 , wherein said etch stop layer is comprised of silicon nitride and said first and second layers of insulating material are comprised of silicon dioxide. 
     
     
         6 . The FinFET device of  claim 1 , wherein said etch stop layer is comprised of silicon nitride. 
     
     
         7 . The FinFET device of  claim 5 , wherein said first layer of insulating material is comprised of silicon dioxide. 
     
     
         8 . The FinFET device of  claim 1 , further comprising a second semiconductor material positioned on at least a portion of said fin, wherein said metal silicide region is further positioned on all surfaces of said second semiconductor material. 
     
     
         9 . The FinFET device of  claim 6 , wherein at least a portion of a perimeter of said second semiconductor material has a substantially diamond-shaped configuration. 
     
     
         10 . The FinFET device of  claim 1 , further comprising a conductive contact structure that is positioned above said etch stop layer in at least one of said plurality of spaced-apart trenches and conductively coupled to said fin. 
     
     
         11 . The FinFET device of  claim 1 , wherein said fin is a first fin and said plurality of spaced-apart trenches at least partially define a second fin laterally adjacent to and spaced apart from said first fin, a first trench of said plurality of spaced-apart trenches being positioned between said first and second fins. 
     
     
         12 . The FinFET device of  claim 11 , wherein said upper surface of said etch stop layer positioned in said first trench has a first edge defined by a first interface wherein said upper surface contacts a first sidewall of said first fin and a second edge defined by a second interface wherein said upper surface contacts a second sidewall of said second fin, said etch stop layer positioned in said first trench having a substantially uniform thickness between said first edge and said second edge in a direction that is normal to said bottom surface of said first trench. 
     
     
         13 . A FinFET device, comprising:
 a plurality of spaced-apart trenches in a semiconducting substrate, said plurality of spaced-apart trenches at least partially defining a fin for said FinFET device, wherein said fin comprises a first semiconductor material;   a second semiconductor material positioned on an upper portion of said fin;   a first layer of insulating material positioned on a bottom surface of each of said plurality of spaced-apart trenches;   an etch stop layer positioned on said first layer of insulating material within each of said plurality of spaced-apart trenches;   a gate structure positioned on and around said fin; and   a metal silicide region positioned on all surfaces of said second semiconductor material and on all sidewall surfaces of said fin between an upper surface of said etch stop layer and said second semiconductor material.   
     
     
         14 . The FinFET device of  claim 13 , wherein said gate structure extends across at least one of said plurality of spaced-apart trenches, the FinFET device further comprising a second layer of insulating material positioned between a portion of said etch stop layer positioned within each of said plurality of spaced-apart trenches and a sidewall spacer positioned adjacent to sidewalls of said gate structure. 
     
     
         15 . The FinFET device of  claim 14 , wherein said etch stop layer is comprised of silicon nitride and said first and second layers of insulating material are comprised of silicon dioxide. 
     
     
         16 . The FinFET device of  claim 13 , wherein at least a portion of a perimeter of said second semiconductor material has a substantially diamond-shaped configuration. 
     
     
         17 . The FinFET device of  claim 13 , further comprising a conductive contact structure that is positioned above said etch stop layer in each of said plurality of spaced-apart trenches and conductively coupled to said fin. 
     
     
         18 . The FinFET device of  claim 13 , wherein said fin is a first fin and said plurality of spaced-apart trenches at least partially define a second fin laterally adjacent to and spaced apart from said first fin, wherein said gate structure is further positioned on and around said second fin and extends from said first fin to said second fin across a first trench of said plurality of spaced-apart trenches. 
     
     
         19 . The FinFET device of  claim 18 , wherein substantially an entirety of said upper surface of said etch stop layer positioned in first trench is in a plane that is defined by a first edge wherein said upper surface terminates at a first sidewall of said first fin and a second edge wherein said upper surface terminates at a second sidewall of said second fin. 
     
     
         20 . A FinFET device, comprising:
 a plurality of spaced-apart trenches in a semiconducting substrate, said plurality of spaced-apart trenches at least partially defining a plurality of fins for said FinFET device, each of said plurality of fins comprising a first semiconductor material;   a second semiconductor material positioned on an upper portion of each of said plurality of fins;   a first layer of insulating material positioned above a bottom surface of each of said plurality of spaced-apart trenches and extending between adjacent sidewalls of each adjacent pair of said plurality of fins;   an etch stop layer positioned on said first layer of insulating material in each of said plurality of spaced-apart trenches and extending between said respective adjacent sidewalls of said each adjacent pair of said plurality of fins, wherein said etch stop layer positioned in each of said plurality of spaced-apart trenches has a substantially uniform thickness between said respective adjacent sidewalls in a direction that is normal to said bottom surface of said respective trench;   a gate structure positioned on and extending continuously over each of said plurality of fins;   a sidewall spacer positioned adjacent to sidewalls of said gate structure;   a second layer of insulating material positioned between a portion of said etch stop layer positioned in each of said plurality of spaced-apart trenches and said sidewall spacer; and   a metal silicide region positioned on all surfaces of said second semiconductor material positioned on said upper portion of each of said plurality of fins and on all sidewall surfaces of each of said plurality of fins between an upper surface of said etch stop layer and said second semiconductor material.