Electroless filled conductive structures

Abstract

Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a dielectric layer configured with a recess having sidewalls and a bottom area;   electroless nucleation material at the bottom area of the recess;   electroless suppression material on the sidewalls of the recess but not covering the bottom area of the recess; and   electroless fill metal disposed in the recess on the electroless nucleation material and the electroless suppression material.