Serial connection external interface riser cards avoidance of abutment of parallel connection external interface memory modules

Abstract

A first riser card of an apparatus in an example substantially axially connects with a first serial connection external interface of a printed circuit board (PCB) and at least in part laterally connects with a parallel connection external interface of a first memory module. The first riser card supports the first memory module with avoidance of abutment of the first memory module with a second memory module supported by a second riser card that is adjacent to the first riser card.

What is claimed is: 
     
         1 . A process, comprising:
 performing an upgrade of a serial memory implementation within a printed circuit board (PCB) to a parallel memory implementation outside the PCB through employment of a first riser card plugged into a first serial connection external interface of the PCB, wherein the first riser card is to support a first memory module that employs the parallel memory implementation.   
     
     
         2 . The process of  claim 1 , comprising:
 providing the PCB to a user as a field deployment of the PCB with a fixed distance between the first serial connection external interface of the PCB and a second serial connection external interface of the PCB; and   plugging the first riser card into the first serial connection external interface of the PCB after the field deployment of the PCB to the user.   
     
     
         3 . The process of  claim 1 , comprising:
 plugging the first riser card into the first serial connection external interface with avoidance of abutment of the first memory module with a second memory module supported by an adjacent riser card.   
     
     
         4 . The process of  claim 1 , comprising selecting between a serial memory implementation and a parallel memory implementation for each serial connection external interface of the PCB. 
     
     
         5 . The process of  claim 1 , wherein the PCB comprises at least one connector and voltage regulator module. 
     
     
         6 . The process of  claim 1 , wherein the first riser card and a parallel protocol memory module replace the first serial connection external interface of the PCB. 
     
     
         7 . The process of  claim 1 , wherein a number of pins of the first riser card enable the first riser card to plug directly into a memory module of the serial connection external interface of the PCB. 
     
     
         8 . A process, comprising:
 performing an upgrade of a serial memory implementation within a printed circuit board (PCB) to a parallel memory implementation outside the PCB through employment of a translator riser card plugged into a first serial connection external interface of the PCB while maintaining a second serial connection external interface of the PCB, wherein the translator riser card is to support a first memory module and the second serial connection is to support a second memory module.   
     
     
         9 . The process of  claim 8 , wherein the translator riser card includes a notch at both ends of the translator riser card. 
     
     
         10 . The process of  claim 9 , wherein the notch at both ends of the translator riser card is accommodated by an end latch of the first serial connection external interface. 
     
     
         11 . The process of  claim 8 , wherein the PCB includes a single serial memory architecture. 
     
     
         12 . A process, comprising:
 performing an upgrade of a serial memory implementation within a printed circuit board (PCB) to a parallel memory implementation outside the PCB through employment of a translator riser card plugged directly into each serial connection external interface of the PCB, wherein the translator riser card is to support a corresponding memory module for each serial connection external interface of the PCB.   
     
     
         13 . The process of  claim 12 , wherein the translator riser card is to plug directly into a FB-DIMM memory architecture. 
     
     
         14 . The process of  claim 13 , wherein the translator riser card is to enable a DDR3 SDRAM DIMM memory architecture to be utilized with the FB-DIMM memory architecture. 
     
     
         15 . The process of  claim 14 , wherein a memory bandwidth of the FB-DIMM memory architecture and the DDR3 SDRAM DIMM memory architecture are maintained.