US2016020215A1PendingUtilityA1

Semiconductor structure

Assignee: SEMICONDUCTOR MFG INT SHANGHAIPriority: Oct 31, 2012Filed: Sep 30, 2015Published: Jan 21, 2016
Est. expiryOct 31, 2032(~6.3 yrs left)· nominal 20-yr term from priority
H10W 20/20H10W 10/17H10W 10/014H10W 20/493H10D 62/115H01L 23/535H01L 29/0649H01L 27/11206H10B 20/25
43
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Claims

Abstract

Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each of the protective layer and the high-K dielectric layer can be removed from the fuse region to expose the STI structure. A fuse layer can be formed on the exposed surface of the STI structure. A portion of the fuse layer, the remaining portion of the protective layer, and a remaining portion of the high-K dielectric layer outside of the fuse region can be removed from the semiconductor substrate to form a fuse structure.

Claims

exact text as granted — not AI-modified
1 .- 14 . (canceled) 
     
     
         15 . A semiconductor structure, comprising:
 a semiconductor substrate including a shallow trench isolation (STI) structure formed therein, the STI structure including a fuse region;   a high-K dielectric layer disposed on the semiconductor substrate outside of the fuse region;   a protective layer disposed on the high-K dielectric layer; and   a fuse structure including a fuse layer disposed on the STI structure in the fuse region and in direct contact with a surface of the STI structure.   
     
     
         16 . The structure of  claim 15 , further including a transistor disposed on a surface portion of the semiconductor substrate, wherein the transistor includes a gate dielectric layer including the high-K dielectric layer, and a gate electrode layer including a metal. 
     
     
         17 . The structure of  claim 16 , wherein the transistor is formed by forming a dummy gate structure while simultaneously forming the fuse structure, wherein the dummy gate structure includes a fuse layer disposed on a portion of each of the protective layer and the high-K dielectric layer on the semiconductor substrate. 
     
     
         18 . The structure of  claim 15 , wherein the fuse layer is made of polycrystalline silicon or polycrystalline germanium; the protective layer is made of titanium nitride, tantalum nitride, or a combination thereof; and the STI structure is made of silicon oxide. 
     
     
         19 . The structure of  claim 15 , wherein the fuse layer in the fuse structure includes:
 a cathode at one end and an anode at another end of the fuse layer, and   a blowing area between the cathode and the anode.   
     
     
         20 . The structure of  claim 15 , further including a plurality of conductive plugs connected with a surface of each of the cathode and the anode, wherein the plurality of conductive plugs are made of a material including copper, tungsten, aluminum, or a combination thereof. 
     
     
         21 . The structure of  claim 19 , wherein:
 the blowing area has a width less than at least one of the cathode and the anode;   
     
     
         22 . The structure of  claim 19 , wherein:
 the cathode has a rectangle shape and the anode has a trapezoid shape.   
     
     
         23 . The structure of  claim 19 , wherein:
 the fuse layer is doped with p-type ions or n-type ions.

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