Device and method for controlling the turn-off of a solid state switch (sgto)

Abstract

A circuit for turning OFF a thyristor. The circuit includes at least one first circuit element configured to provide a high reverse turn-OFF voltage to the thyristor gate for a predetermined period of time. Immediately following the predetermined period of time, at least one second circuit element provides a normal reverse turn-OFF voltage to the thyristor gate. The normal reverse turn-OFF voltage is substantially lower than the high reverse turn-OFF voltage.

1 . A circuit for turning OFF a thyristor having a gate, said circuit comprising:
 at least one first circuit element configured to provide a first reverse turn-OFF voltage to the thyristor gate; and   at least one second circuit element configured to provide a second reverse turn-OFF voltage to the thyristor gate, wherein the second reverse turn-OFF voltage is different from the first reverse turn-OFF voltage.   
     
     
         2 . The circuit of  claim 1 , wherein the second reverse turn-OFF voltage is about −9 volts, and the first reverse turn-OFF voltage is about −18 volts. 
     
     
         3 - 4 . (canceled) 
     
     
         5 . The circuit of  claim 1 , wherein the at least one first circuit element comprises at least one transistor. 
     
     
         6 . The circuit of  claim 1 , wherein the at least one second circuit element comprises at least one transistor. 
     
     
         7 . The circuit of  claim 1 , wherein the at least one first circuit element comprises a first and the at least one second circuit element comprises a second-switch. 
     
     
         8 . The circuit of  claim 1 , wherein the gate of the thyristor does not enter avalanche mode. 
     
     
         9 . (canceled) 
     
     
         10 . The circuit of  claim 1 , wherein the first reverse turn-OFF voltage substantially reduces current in the thyristor. 
     
     
         11 . A method for turning OFF a thyristor having a gate, said method comprising:
 providing by at least one first circuit element a high first reverse turn-OFF voltage to the thyristor gate; and   providing by at least one second circuit element a second reverse turn-OFF voltage to the thyristor gate, wherein the second reverse turn-OFF voltage is different from the first reverse turn-OFF voltage.   
     
     
         12 . A circuit for turning OFF a thyristor having a gate and a cathode, said circuit comprising:
 a low reverse gate voltage power supply;   a high reverse gate voltage power supply;   a first switch connected to the thyristor gate and the low reverse gate voltage power supply;   a second switch connected to the thyristor cathode and the high reverse gate voltage power supply;   a third switch connected to the thyristor gate; and   a fourth switch connected to the thyristor cathode;   wherein said circuit provides a high reverse turn-OFF voltage to the thyristor gate for a predetermined period of time when the first and fourth switches are OFF and the second and third switches are ON; and   wherein said circuit provides a normal reverse turn-OFF voltage to the thyristor gate immediately following the predetermined period of time when the third and fourth switches are OFF and the first and second switches are ON.   
     
     
         13 . The method of  claim 11 , wherein the providing of the second reverse turn-OFF voltage is performed after the providing of the first reverse turn-OFF voltage. 
     
     
         14 . The method of  claim 11 , wherein the providing of the second reverse turn-OFF voltage is performed immediately following the providing of the first reverse turn-OFF voltage. 
     
     
         15 . The method of  claim 11 , wherein the second reverse turn-OFF voltage is lower than the first reverse turn-OFF voltage. 
     
     
         16 . The method of  claim 11 , wherein the second reverse turn-OFF voltage is 50% lower than the first reverse turn-OFF voltage. 
     
     
         17 . The method of  claim 11 , wherein the second reverse turn-OFF voltage is substantially lower than the first reverse turn-OFF voltage. 
     
     
         18 . The circuit of  claim 1 , wherein the at least one second circuit element is configured to provide the second reverse turn-OFF voltage after the at least one first circuit element provides the first reverse turn-OFF voltage. 
     
     
         19 . The circuit of  claim 1 , wherein the second reverse turn-OFF voltage is lower than the first reverse turn-OFF voltage. 
     
     
         20 . The circuit of  claim 1 , wherein the second reverse turn-OFF voltage is 50% lower than the first reverse turn-OFF voltage. 
     
     
         21 . The circuit of  claim 1 , wherein the second reverse turn-OFF voltage is substantially lower than the first reverse turn-OFF voltage. 
     
     
         22 . The circuit of  claim 1 , wherein: 
 the at least one first circuit element is configured to provide the first reverse turn-OFF voltage to the thyristor gate for a predetermined period of time; and   the at least one second circuit element is configured to provide the second reverse turn-OFF voltage to the thyristor gate following the predetermined period of time.   
     
     
         23 . The circuit of  claim 22 , wherein the thyristor further comprises a cathode and a gate-cathode junction, wherein the predetermined period of time is a time over which the gate-cathode junction does not block the first reverse turn-OFF voltage and then, if it does block the first reverse turn-OFF voltage, a further time over which the thyristor can dissipate avalanche power. 
     
     
         24 . The circuit of  claim 22 , wherein the predetermined period of time is less than about 5 microseconds. 
     
     
         25 . The circuit of  claim 22 , wherein the predetermined period of time is  2  microseconds. 
     
     
         26 . The circuit of  claim 22 , wherein the second reverse turn-OFF voltage immediately follows the predetermined period of time.