Method for manufacturing cmos structure

Abstract

The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.

What is claimed is: 
     
         1 . A method for manufacturing a CMOS structure, comprising:
 forming a first gate stack on a semiconductor substrate in a first region;   forming a second gate stack on said semiconductor substrate in a second region;   implanting a dopant of a first type with said first gate stack and said second gate stack as a hard mask, to form a lightly-doped drain region of said first type; and   implanting a dopant of a second type by using a first mask and with said second gate stack as a hard mask, to form a lightly-doped drain region of said second type, wherein said first mask blocks said first region and exposes said second region,   wherein when said lightly-doped drain region of said second type is formed, said dopant of said second type over dopes a predetermined region of said lightly-doped drain region of said first type.   
     
     
         2 . The method according to  claim 1 , wherein each of said first gate stack and said second gate stack comprises a gate conductor and a gate dielectric, and said gate dielectric is disposed between said gate conductor and said semiconductor substrate. 
     
     
         3 . The method according to  claim 2 , wherein said gate conductor is made of polysilicon. 
     
     
         4 . The method according to  claim 3 , after said steps of forming said first gate stack and forming said second gate stack, further comprising doping said gate conductor of at least one of said first gate stack and said second gate stack to adjust work function. 
     
     
         5 . The method according to  claim 1 , before said step of forming said first gate stack, further comprising at least one of:
 forming a first well region of said second type by implanting a dopant of said second type in said first region of said semiconductor substrate; and   forming a second well region of said first type by implanting said dopant of said first type in said second region of said semiconductor substrate.   
     
     
         6 . The method according to  claim 5 , wherein at least one of said first well region and said second well region has a doping concentration which is controlled in view of a threshold voltage. 
     
     
         7 . The method according to  claim 1 , before said step of forming said first gate stack, further comprising:
 forming shallow trench isolation in said semiconductor substrate for defining said first region for MOSFETs of said first type and said second region for MOSFETs of said second type.   
     
     
         8 . The method according to  claim 1 , after said steps of forming said first gate stack and forming said second gate stack, and before said steps of forming said lightly-doped drain region of said first type and forming said lightly-doped drain region of said second type, further comprising forming gate spacers on side walls of said first gate stack and said second gate stack. 
     
     
         9 . The method according to  claim 1 , after said steps of forming said lightly-doped drain region of said first type and forming said lightly-doped drain region of said second type, further comprising forming gate spacers on side walls of said first gate stack and said second gate stack. 
     
     
         10 . The method according to  claim 1 , after said steps of forming said first gate stack and forming said second gate stack, and after said step of forming said lightly-doped drain region of said first type, and before said step of forming said lightly-doped drain region of said second type, further comprising forming gate spacers on side walls of said first gate stack and said second gate stack. 
     
     
         11 . The method according to  claim 9 , further comprising:
 implanting a dopant of said first type by using a second mask and with said first gate stack and said gate spacers as a hard mask, to form source/drain regions of said first type, wherein said second mask blocks said second region and exposes said first region; and   implanting a dopant of said second type by using a third mask and with said second gate stack and said gate spacers as a hard mask, to form source/drain regions of said second type, wherein said third mask blocks said first region and exposes said second region.   
     
     
         12 . The method according to  claim 10 , further comprising:
 implanting a dopant of said second type by using said first mask and with said second gate stack and said gate spacers as a hard mask, to form said lightly-doped drain region of said second type and source/drain regions of said second type, wherein said first mask blocks said first region and exposes said second region, and   implanting a dopant of said first type by using a second mask and with said first gate stack and said gate spacers as a hard mask, to form source/drain regions of said first type, wherein said second mask blocks said second region and exposes said first region.   
     
     
         13 . The method according to  claim 12 , further comprising implanting a dopant of said second type by angled ion implantation through said gate spacers to form said lightly-doped drain region of said second type. 
     
     
         14 . The method according to  claim 1 , after said steps of forming said source/drain regions of said first type and forming said source/drain regions of said second type, further comprising:
 performing silicidation to form a metal silicide layer on said source/drain regions of said first type, on said source/drain regions of said second type, and on said gate stack.   
     
     
         15 . The method according to  claim 2 , wherein said gate conductor of said first gate stack contains a dopant of said first type, and said gate conductor of said second gate stack contains a dopant of said first type and a dopant of said second type.