Methods of manufacturing semiconductor devices

Abstract

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

1 .- 16 . (canceled) 
     
     
         17 . A method of manufacturing a semiconductor device, the method comprising:
 preparing a substrate including a cell region and a peripheral region;   defining cell active portions in the cell region and a peripheral active portion in the peripheral region;   forming cell gate electrodes respectively buried in grooves crossing the cell active portions;   forming an insulating layer on the cell active portions and the peripheral active portion;   forming a conductive layer on an entire surface of the substrate having the insulating layer;   forming a hard mask layer on the conductive layer;   forming cell line patterns by performing a cell patterning process on the hard mask layer and the conductive layer in the cell region; and   forming a peripheral gate pattern by performing a peripheral patterning process on the hard mask layer and the conductive layer in the peripheral region,   wherein, after one of the cell and peripheral patterning processes is performed, the other of the cell and peripheral patterning processes is performed.   
     
     
         18 . The method as claimed in  claim 17 , wherein forming the conductive layer includes:
 forming a lower conductive layer on the entire surface of the substrate having the insulating layer;   forming a contact plug successively penetrating the lower conductive layer and the insulating layer in the cell region, the contact plug being connected to a first source/drain region formed in each of the cell active portions at a side of the cell gate electrode; and   forming an upper conductive layer on the contact plugs and the lower conductive layer.   
     
     
         19 . The method as claimed in  claim 17 , wherein the cell patterning process is performed after the peripheral patterning process is performed. 
     
     
         20 . The method as claimed in  claim 19 , wherein, before performing the cell patterning process, further comprising:
 forming an interlayer insulating layer an entire surface of the substrate having the peripheral gate pattern; and   planarizing the interlayer insulating layer to remove the interlayer insulating layer on the hard mask layer in the cell region and to leave the planarized interlayer insulating layer in the peripheral region.   
     
     
         21 . The method as claimed in  claim 20 , wherein, before performing the cell patterning process, further comprising forming a capping insulating layer on the entire surface of the substrate having the planarized interlayer insulating layer. 
     
     
         22 . The method as claimed in  claim 21 , wherein performing the cell patterning process includes:
 successively patterning the capping insulating layer, the hard mask layer, and the conductive layer in the cell region to form the cell line patterns and capping line patterns,   wherein the capping line patterns are disposed on top surfaces of the cell line patterns, respectively; and   wherein the capping insulating layer in the peripheral region remains after the cell patterning process is performed.   
     
     
         23 . The method as claimed in  claim 19 , wherein the hard mask layer and the conductive layer in the cell region are successively patterned to form a plate pattern covering all of the cell active portions when the peripheral patterning process is performed, and
 wherein the cell patterning process is performed on the hard mask layer and the conductive layer which are included in the plate pattern.   
     
     
         24 . The method as claimed in  claim 23 , wherein the cell patterning process uses cell line mask patterns crossing over the plate pattern as etch masks,
 wherein end portions of a pair of the cell line mask patterns adjacent to each other are respectively connected to both ends of a connection part formed of the same material as the cell line mask patterns, and   wherein the connection part is disposed beyond a top surface of the plate pattern in plan view.   
     
     
         25 . The method as claimed in  claim 23 , further comprising forming a peripheral gate spacer on a sidewall of the peripheral gate pattern,
 wherein a spacer is formed on a sidewall of the plate pattern when the peripheral gate spacer is formed,   wherein the spacer on the sidewall of the plate pattern is formed of a same material as the peripheral gate spacer, and   wherein the spacer remains on an outer sidewall of an outermost one of the cell line patterns.   
     
     
         26 . The method as claimed in  claim 19 , wherein, after performing the cell patterning process, further comprising:
 conformally forming a cell insulation liner on the entire surface of the substrate;   forming a filling insulation layer filling spaces between the cell line patterns on the cell insulation liner; and   planarizing the filling insulation layer to remove the filling insulation layer in the peripheral region and to leave the planarized filling insulation layer filling the spaces in the cell region.   
     
     
         27 . The method as claimed in  claim 17 , wherein the peripheral pattern process is performed after the cell patterning process is performed. 
     
     
         28 . The method as claimed in  claim 27 , wherein, before performing the peripheral patterning process, further comprising:
 conformally forming a cell insulation liner on the entire surface of the substrate;   forming a filling insulation layer filling spaces between the cell line patterns on the cell insulation liner; and   planarizing the filling insulation layer to remove the filling insulation layer in the peripheral region and to leave the planarized filling insulation layer filling the spaces in the cell region.   
     
     
         29 . The method as claimed in  claim 28 , wherein, before performing the peripheral patterning process, further comprising:
 forming a capping insulating layer on the entire surface of the substrate having the planarized filling insulation layer,   wherein performing the peripheral patterning process includes successively patterning the capping insulating layer, the hard mask layer, and the conductive layer in the peripheral region, and   wherein, after the peripheral patterning process is performed, the capping insulating layer in the cell region is removed to expose the planarized filling insulation layer.   
     
     
         30 . The method as claimed in  claim 27 , wherein, after performing the peripheral patterning process, further comprising:
 forming an interlayer insulating layer on the entire surface of the substrate; and   planarizing the interlayer insulating layer to remove the interlayer insulating layer in the cell region and to leave the planarized interlayer insulating layer in the peripheral region.   
     
     
         31 . A method of manufacturing a semiconductor device, the method comprising:
 sequentially forming a conductive layer and a hard mask layer on a substrate including a first region and a second region;   patterning the hard mask layer and the conductive layer in the first region to form a first pattern;   forming a first insulating layer covering the first pattern on an entire surface of the substrate;   planarizing the first insulating layer to leave the planarized first insulating layer around the first pattern and to remove the first insulating layer on the hard mask layer in the second region; and   after planarizing the first insulating layer, patterning the hard mask layer and the conductive layer in the second region to form a second pattern.   
     
     
         32 . The method as claimed in  claim 31 , further comprising:
 after forming the second pattern, forming a second insulating layer on the entire surface of the substrate; and   planarizing the second insulating layer.   
     
     
         33 . A method of manufacturing a semiconductor device, the method comprising:
 defining cell active portions in a cell region of a substrate and a peripheral active portion in a peripheral region of the substrate;   forming cell gate electrodes in grooves intersecting the cell active portions;   forming an insulating layer on the cell active portions and the peripheral active portion;   forming a conductive layer on the insulating layer;   forming a hard mask layer on the conductive layer;   patterning the hard mask layer and the conductive layer in the cell region, such that cell line patterns are formed in the cell region; and   patterning the hard mask layer and the conductive layer in the peripheral region, such that a peripheral gate pattern is formed in the peripheral region,   wherein process conditions during patterning in the cell region are independent of process conditions during patterning in the peripheral region.   
     
     
         34 . The method as claimed in  claim 33 , wherein patterning of the cell region and patterning of the peripheral region are not simultaneous. 
     
     
         35 . The method as claimed in  claim 34 , wherein patterning of one of the cell region and the peripheral region begins only after patterning of the other one of the cell region and the peripheral region is completed. 
     
     
         36 . The method as claimed in  claim 33 , wherein patterning of the cell and peripheral regions includes patterning the hard mask layer and the conductive layer, a combined profile of the hard mask layer and the conductive layer in each of the cell and peripheral regions being different from each other. 
     
     
         37 . (canceled)