Method and apparatus for writing data to non-volatile memory

Abstract

Devices and methods implemented therein are disclosed for storing data in memory pages of a non-volatile memory of the storage device. The device comprises a non-volatile memory, a reading circuit, a programming circuit and a read disturb detector. The non-volatile memory has an erased memory page comprising a plurality of multi-layer cells (MLCs). The reading circuit is configured to read a respective electric charge stored in each of the plurality of MLCs. The programming circuit is configured to store data in the plurality of MLCs at either one of a first storage density or a second storage density. The read disturb detector is configured to determine whether the erased memory page is read disturbed and if the erased memory page is read disturbed, cause the programming circuit to store data into the MLCs at the second storage density that is less than the first storage density.

We claim: 
     
         1 . A method for writing data in a memory system having a non-volatile memory, the method comprising:
 identifying a memory page in the non-volatile memory that is erased, wherein the memory page comprises a set of memory cells and wherein the memory page is configured to store X times N bits of data where X is a number of memory cells comprising the memory page and where N is an integer number of bits that can be stored in each of the set of memory cells;   determining a number of read disturbed memory cells in the memory page, wherein a read disturbed memory cell contains an electric charge between a first and second predetermined threshold; and   in response to determining that the number of read disturbed memory cells of the memory page exceeds a threshold number, writing X times M bits of data to the memory page, wherein M is an integer and M<N and M>0.   
     
     
         2 . The method of  claim 1  further comprising:
 identifying the memory page in response to receiving a request to write the data from a host device. 
 
     
     
         3 . The method of  claim 2  wherein determining the number of read disturbed memory cells comprising determining a respective voltage level from each of the memory cells wherein each of the respective voltage levels corresponds to the respective electric charge stored in each of the respective set of memory cells. 
     
     
         4 . The method of  claim 3  further comprising comparing each of the respective voltage levels with a first voltage threshold and a second voltage threshold and wherein the first predetermined threshold corresponds to the first voltage threshold and the second predetermined threshold corresponds to the second voltage threshold. 
     
     
         5 . The method of  claim 4  further comprising computing a fraction of the determined number of read disturbed memory cells and the number of memory cells. 
     
     
         6 . The method of  claim 5  wherein determining that the number of read disturbed memory cells of the memory page exceeds the threshold number comprises comparing the computed fraction with the threshold number wherein the threshold number is between 0 and 0.1. 
     
     
         7 . A method for writing data in a memory system, the memory system comprising an erased memory page having a set of multi-layer cells (MLCs), wherein the set of MLCs have a first storage density, the method comprising:
 in response to receiving a request to store data, determining a number of MLCs in the set of MLCs that exceed a voltage threshold; and   in response to determining that the number of MLCs exceeding the voltage threshold is above a threshold number of MLCs, storing a portion of the received data in the set of MLCs at a second storage density, wherein the second storage density is less than the first storage density.   
     
     
         8 . The method of  claim 7  further comprising receiving the request to write data from a host device. 
     
     
         9 . The method of  claim 7  further comprising identifying a second erased memory block to store a portion of the received data not stored in the erased memory block and storing the portion of the received data not stored in the erased memory block in the second erased memory block. 
     
     
         10 . The method of  claim 7  further comprising in response to determining that a number of MLCs in the set of MLCs exceeding a second voltage threshold is above the threshold number of MLCs, identifying a second erased memory page to store the data. 
     
     
         11 . The method of  claim 10  further comprising storing default data in the erased memory page. 
     
     
         12 . The method of  claim 7  wherein determining the number of MLCs in the set of MLCs that exceed the voltage threshold comprises determining a respective electric charge stored in each of the MLCs. 
     
     
         13 . A device comprising:
 a non-volatile memory having an erased memory page comprising a plurality of multi-layer cells (MLCs);   a reading circuit configured to read a respective electric charge stored in each of the plurality of MLCs of the erased memory page;   a programming circuit configured to store data in the plurality of MLCs at either one of a first storage density or a second storage density; and   a read disturb detector configured to, based on respective electric charges read from the MLCs, determine whether the erased memory page is read disturbed and, in response to determining that the erased memory page is read disturbed, cause the programming circuit to store data into the MLCs at the second storage density, wherein the second storage density is less than the first storage density.   
     
     
         14 . The device of  claim 13 , wherein to determine whether the erased memory page is read disturbed, the read disturb detector is further configured to determine whether a number of MLCs in the plurality of MLCs having an electric charge exceeding a voltage threshold is above a threshold number of MLCs. 
     
     
         15 . The device of  claim 13 , wherein the plurality of MLCs are adapted to store 3 bits of data per MLC and wherein the read disturb detector in response to determining that the erased memory page is read disturbed is configured to cause the programming circuit to store either 1 or 2 bits of data per MLC, wherein 3 bits of data per MLC corresponds to the first storage density and either 1 or 2 bits of data per MLC corresponds to the second storage density. 
     
     
         16 . The device of  claim 14  wherein to determine whether the erased memory page is read disturbed, the read disturb detector is further configured to determine whether a number of MLCs in the plurality of MLCs exceeding a second voltage threshold is above the threshold number of MLCs. 
     
     
         17 . The device of  claim 13  wherein the non-volatile memory comprises a three dimensional memory array. 
     
     
         18 . The device of  claim 13  further comprising a host device wherein the host device is configured to communicate data to be stored in the erased memory page. 
     
     
         19 . The device of  claim 14 , wherein the read disturb detector is further configured to cause the programming circuit to store default data in the erased memory page when the number of MLCs in the plurality of MLCs exceeding a second voltage threshold is above the threshold number of MLCs. 
     
     
         20 . The device of  claim 19 , wherein the read disturb detector is further configured to cause erasure of the erased memory page.