Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance

Abstract

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

What is claimed is: 
     
         1 . A method of manufacturing an integrated circuit, comprising:
 forming at least one circuit element comprising a layer of a ferroelectric material near a semiconducting surface of a body;   then forming at least one level of conductors overlying the element, each level comprising patterned metal conductors and a dielectric layer;   forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors;   then depositing a passivation layer over the protective overcoat layer; and   heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than about twenty minutes.   
     
     
         2 . The method of  claim 1 , wherein the ferroelectric material is lead-zirconium-titanate. 
     
     
         3 . The method of  claim 2 , wherein the heating step heats the passivation layer to a curing temperature at or below about 390° C. 
     
     
         4 . The method of  claim 1 , wherein the at least one circuit element comprises a plurality of ferroelectric capacitors;
 and further comprising:
 before the heating step, polarizing the ferroelectric capacitors. 
   
     
     
         5 . The method of  claim 4 , wherein the at least one circuit elements further comprise a plurality of metal-oxide-semiconductor (MOS) transistors, each associated with one of the ferroelectric capacitors in a plurality of memory cells;
 wherein each of the plurality of ferroelectric capacitors comprises first and second parallel conductive plates disposed on either side of the ferroelectric material, the first plate coupled to a plate line conductor in the integrated circuit and the second plate coupled to a source/drain region of its associated MOS transistor;   wherein the polarizing step comprises:
 applying a voltage at or above a coercive voltage across each of the ferroelectric capacitors, at a positive polarity at the first plate relative to the second plate. 
   
     
     
         6 . The method of  claim 1 , wherein the passivation layer comprises a polymer-containing soft stress release material having a low elastic modulus as compared with SiO 2    
     
     
         7 . The method of  claim 6 , wherein the polymer-containing soft stress release material is selected from the group consisting of polyimides, polybenzoxazole (PBO), benzocyclobutene-based polymers (BCB), and fluoro-polymers. 
     
     
         8 . The method of  claim 1 , wherein the passivation layer comprises a polyimide;
 and wherein the heating step comprises:
 exposing the passivation layer to variable frequency microwave energy. 
   
     
     
         9 . The method of  claim 1 , wherein the heating step heats the passivation layer from an ambient temperature to a curing temperature of at least 340° C. and below the Curie temperature of the ferroelectric material at a ramp rate of at least 0.40° C. per second. 
     
     
         10 . The method of  claim 1 , wherein the heating step maintains the passivation layer at the curing temperature for a maximum duration of about ten minutes. 
     
     
         11 . The method of  claim 1 , wherein, after the exposing step, the passivation layer cools from the curing temperature at a ramp rate of at least about 0.40° C. per second. 
     
     
         12 . The method of  claim 1 , wherein the step of forming at least one level of conductors comprises:
 depositing a barrier layer comprising silicon nitride;   then depositing a metallization layer comprising copper; and   then removing selected portions of the metallization layer to define the conductors.   
     
     
         13 . An integrated circuit, comprising:
 at least one circuit element comprising a layer of a ferroelectric material, and disposed near a semiconducting surface of a body;   at least one layer of insulating material disposed over the surface and overlying the at least one circuit element;   at least one level of conductors disposed near the surface;   a protective overcoat layer, comprising an insulating material, disposed over the ferroelectric circuit element, the at least one layer of insulating material, and the at least one level of conductors; and   a passivation layer overlying the protective overcoat layer, the passivation layer having a tensile stress state, and formed by a process comprising:
 heating the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state, and of less than about twenty minutes. 
   
     
     
         14 . The integrated circuit of  claim 13 , further comprising:
 a plurality of solder balls near the surface, in contact with conductors through openings in the passivation layer.   
     
     
         15 . The integrated circuit of  claim 13 , wherein the passivation layer comprises a polymer-containing soft stress release material having a low elastic modulus as compared with SiO 2    
     
     
         16 . The integrated circuit of  claim 15 , wherein the polymer-containing soft stress release material is selected from the group consisting of polyimides, polybenzoxazole (PBO), benzocyclobutene-based polymers (BCB), and fluoro-polymers. 
     
     
         17 . The integrated circuit of  claim 13 , wherein the at least one circuit element comprises a plurality of ferroelectric capacitors, each comprising first and second parallel conductive plates disposed on either side of the ferroelectric material. 
     
     
         18 . The integrated circuit of  claim 17 , wherein the at least one circuit elements further comprise a plurality of metal-oxide-semiconductor (MOS) transistors, each associated with one of the ferroelectric capacitors in a plurality of memory cells;
 and wherein each of the plurality of ferroelectric capacitors comprises first and second parallel conductive plates disposed on either side of the ferroelectric material, the first plate coupled to a plate line conductor in the integrated circuit and the second plate coupled to a source/drain region of its associated MOS transistor.   
     
     
         19 . A method of manufacturing an integrated circuit, comprising:
 forming at least one circuit element comprising a layer of a ferroelectric material near a semiconducting surface of a body;   then forming at least one level of conductors overlying the element, each level comprising patterned metal conductors and a dielectric layer;   forming a protective overcoat layer over the surface and overlying the at least one circuit element and the at least one level of conductors;   then depositing a passivation layer of a material comprising a polymer-containing film over the protective overcoat layer; and   applying electromagnetic energy to the passivation layer at a frequency corresponding to a vibrational frequency of the polymer, to heat the passivation layer to a temperature below a Curie temperature of the ferroelectric material for a duration sufficient to cure the material of the passivation layer into a tensile stress state.   
     
     
         20 . The method of  claim 19 , wherein the step of applying electromagnetic energy heats the passivation layer is performed for a duration of less than about twenty minutes.