Programmable Devices and Methods of Manufacture Thereof

Abstract

Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming an isolation region within a substrate;   forming a link over the isolation region, the link having a first end, a second end, and sidewalls;   forming a silicide on the link and on portions of the substrate proximate the link;   forming at least one first contact coupled to the first end and sidewalls of the link and to a portion of the substrate;   forming at least one second contact coupled to the second end and sidewalls of the link and to a portion of the substrate;   forming a first conductive line over the at least one first contact; and   forming a second conductive line over the at least one second contact.   
     
     
         2 . The method according to  claim 1 , wherein forming the at least one first contact and the at least one second contact comprises:
 forming a first insulating material over the link;   patterning the first insulating material proximate the first end and the second end of the link, exposing the first end and the second end of the link and portions of the substrate proximate the first end and the second end of the link; and   disposing a conductive material over the patterned first insulating material.   
     
     
         3 . The method according to  claim 1 , wherein the semiconductor device comprises a minimum feature size, and wherein forming the link comprises forming a link comprising a central region that comprises the minimum feature size of the semiconductor device. 
     
     
         4 . The method according to  claim 3 , wherein forming the link, forming the at least one first contact, forming the at least one second contact, forming the first conductive line, and forming the second conductive line comprise forming a fuse in a first region of the semiconductor device, wherein forming the at least one first contact and forming the at least one second contact comprise forming contacts comprising a substantially rectangular shape in a top view of the semiconductor device, further comprising forming at least one static random access memory (SRAM) device in a second region of the semiconductor device, wherein forming the at least one first contact and forming the at least one second contact further comprises forming at least one third contact of the SRAM device in the second region, the at least one third contact comprising a substantially rectangular shaped contact (CAREC) in the top view of the semiconductor device. 
     
     
         5 . The method according to  claim 1 , wherein forming the at least one first contact or forming the at least one second contact comprises forming a silicide on a sidewall of the link. 
     
     
         6 . The method according to  claim 5 , wherein forming the at least one first contact or forming the at least one second contact comprises forming Ti, wherein forming the link comprises forming Si, and wherein forming the silicide on the sidewall of the link comprises forming TiSi. 
     
     
         7 . A method of manufacturing a semiconductor device, the method comprising:
 forming a silicide layer directly on a region of a substrate;   forming an insulating layer over the substrate;   forming a link comprising a semiconductor or insulator material and a conductive material, wherein the link is formed within the insulating layer, wherein the conductive material is disposed over the semiconductor or insulator material, wherein the link is disposed on the substrate, wherein the link comprises a first sidewall and an opposite second sidewall, and wherein the first sidewall and the second sidewall comprise a silicide sidewall layer covering sidewalls of the semiconductor or insulator material;   forming a first contact in a first opening in the insulating layer, the first contact coupled to a first end of the link, the first contact disposed on and physically contacting the first sidewall of the link, and disposed directly on and physically contacting a first portion of the silicide layer, wherein the first contact comprises a first conductive liner;   forming a second contact in a second opening in the insulating layer, the second contact coupled to a second end of the link, the second contact disposed on the second sidewall of the link;   forming a third contact in a third opening in the insulating layer, the third contact coupled to the first end of the link and disposed adjacent the first contact, the third contact disposed on the first sidewall of the link and disposed directly on and physically contacting the first portion of the silicide layer;   forming a fourth contact in a fourth opening in the insulating layer, the fourth contact coupled to the second end of the link and disposed adjacent the second contact, the fourth contact disposed on the second sidewall of the link.   
     
     
         8 . The method according to  claim 7 , further comprising:
 coupling a first conductive line to the first contact and coupling a second conductive line to the second contact, the first conductive line formed in a metallization level immediately above the first contact, the first conductive line physically contacting a top surface of the first contact.   
     
     
         9 . The method according to  claim 7 , wherein the first contact is formed on a first portion of a top surface of the link, and the second contact is formed on a second portion of the top surface of the link. 
     
     
         10 . The method according to  claim 7 , wherein the first contact and the second contact comprise substantially rectangular shaped contacts in a top view of the programmable device. 
     
     
         11 . The method according to  claim 7 , wherein the first end of the link and the second end of the link are wider than a central region of the link. 
     
     
         12 . The method according to  claim 7 , wherein the semiconductor device comprises a programmable device that is located directly on a shallow trench isolation region. 
     
     
         13 . The method according to  claim 7 , wherein the first contact and the second contact comprise a length on a first edge of about 300 nm or less and a width on a second edge of about 100 nm or less in a top view of the programmable device. 
     
     
         14 . The method according to  claim 7 , wherein the first contact and the second contact comprise W, Cu, Al, Ti, TiN, or TaN. 
     
     
         15 . A method of programming a semiconductor device, the method comprising:
 providing a programmable device, the programmable device comprising a link, at least one first contact coupled to a first end of the link, the at least one first contact being adjacent a portion of a top surface of the link and at least one sidewall of the link, and at least one second contact coupled to a second end of the link, the at least one second contact being adjacent a portion of the top surface of the link and at least one sidewall of the link; and   applying a voltage across the at least one first contact and the at least one second contact, causing a current to flow from the at least one first contact through the link to the at least one second contact.   
     
     
         16 . The method according to  claim 15 , wherein causing the current to flow from the at least one first contact through the link to the at least one second contact alters a resistance of the link of the programmable device. 
     
     
         17 . The method according to  claim 16 , wherein causing the current to flow alters the resistance of the link significantly, so that the resistance may subsequently be sensed to determine a programming state of the programmable device. 
     
     
         18 . The method according to  claim 15 , wherein causing a current to flow from the at least one first contact through the link to the at least one second contact comprises programming the programmable device before a singulation process, after a wafer test, after a burn-in test, after a singulation process, before packaging, after packaging, or during or after a use in an end application. 
     
     
         19 . The method according to  claim 15 , wherein providing the programmable device comprises providing a programmable device wherein the link is disposed over a substrate, wherein a portion of the at least one first contact is coupled to the substrate, wherein causing the current to flow from the at least one first contact through the link to the at least one second contact comprises applying at least a portion of the voltage at the substrate. 
     
     
         20 . The method according to  claim 15 , wherein providing the programmable device comprises providing a programmable device wherein the link comprises a silicide disposed over a material, wherein causing the current to flow from the at least one first contact through the link to the at least one second contact comprises forming a discontinuity in the silicide of the link.