Ldmos transistors for cmos technologies and an associated production method

Abstract

In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region ( 12 ) and the heavily doped feed guiding region ( 28, 28 A), an improved potential profile is achieved in the drain drift region ( 8 ) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.

We claim: 
     
         1 . A semiconductor device comprising:
 a lateral power field effect transistor having a source region of a first conductivity type;   a drain region of the first conductivity type;   a drain drift region of the first conductivity type and having a surface;   a trench isolation region that is at least partially embedded in the drain drift region; and   a doped field guiding region of a second conductivity type;   wherein the second conductivity type is the inverse of the conductivity type.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the doped field guiding region is provided as a region having a freely adjustable potential without an electrical connection. 
     
     
         3 . The semiconductor device of  claim 1 , wherein at least one further field guiding region of the second conductivity type is provided in the drain drift region. 
     
     
         4 . The semiconductor device of any of  claim 1 , wherein the doped field guiding region is directly adjacent to the trench isolation region at an edge that faces the drain region. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a surface of the drain drift region is provided with a layer for preventing the formation of silicide. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the lateral power field effect transistor further comprises a doped body connection region of the second conductivity type directly adjacent to the source region. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the doped body connection region and the doped field guiding region have a same dopant profile in a depth direction thereof. 
     
     
         8 . The semiconductor device of  claim 6 , wherein a maximum dopant concentration of the doped field guiding region is greater than a maximum dopant concentration of the doped body connection region. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a small signal transistor that comprises a deep drain and a source region and a shallow drain and a source extension region of the second conductivity type. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the deep drain and source extension region and the doped field guiding region have a same dopant profile in a depth direction thereof. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the deep drain and source regions and the doped field guiding region have a same dopant profile in a depth direction thereof. 
     
     
         12 . The semiconductor device of  claim 9 , wherein the small signal transistor comprises a gate electrode having a gate length of 200 nm or less. 
     
     
         13 . The semiconductor device of  claim 1 , further comprising:
 a second lateral power field effect transistor having a second source region of the second conductivity type, a second drain region of the second conductivity type, a second drain drift region of the second conductivity type, a second trench isolation region at least partially embedded in the second drain drift region, and at least one second doped field guiding region of the first conductivity type.