Guard ring for memory array

Abstract

A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

What is claimed is: 
     
         1 . A device comprising:
 a substrate having an array region in which memory cells are disposed;   a plurality of storage gates of the memory cells disposed in the array region, wherein each of the storage gates comprises a floating gate and a control gate formed over the floating gate; and   a guard ring surrounding the array region, wherein the guard ring is a storage gate guard ring which includes the same gate and dielectric layers as the storage gates of the memory cells.   
     
     
         2 . The device of  claim 1  wherein the storage gate comprises a storage gate dielectric layer disposed in between the floating and control gates. 
     
     
         3 . The device of  claim 1  wherein the guard ring is displaced away from edge regions of the array region. 
     
     
         4 . The device of  claim 1  wherein the guard ring comprises a width which is uniform throughout all four sides of the guard ring. 
     
     
         5 . The device of  claim 4  wherein the width of the guard ring is about 20 μm. 
     
     
         6 . The device of  claim 1  wherein the guard ring comprises a width which is not uniform throughout all four sides of the guard ring. 
     
     
         7 . The device of  claim 6  wherein longer sides of the guard ring comprise a width dimension which is narrower than shorter sides of the guard ring. 
     
     
         8 . The device of  claim 1  wherein:
 the floating gate comprises a floating gate dielectric layer on the substrate and a floating gate electrode layer on the floating gate dielectric layer; and 
 the storage gate comprises a storage gate dielectric layer in between the floating and control gates. 
 
     
     
         9 . The device of  claim 1  wherein the storage gate includes a hard mask layer and dielectric spacers which are spacer stacks disposed on sidewalls of the storage gate. 
     
     
         10 . The device of  claim 1  further comprising:
 first and second cell terminals which are adjacent to first and second sides of the storage gates, wherein the second cell terminals of adjacent storage gates form a common second cell terminal; and 
 access gates of the memory cells disposed adjacent to the first memory cell terminals of the storage gates. 
 
     
     
         11 . The device of  claim 1  comprising:
 first and second cell terminals which are adjacent to first and second sides of the storage gates, wherein the second cell terminals of adjacent storage gates form a common second cell terminal; and 
 access gates of the memory cells disposed adjacent to the first memory cell terminals and erase gates disposed over the common second cell terminals of the memory cells. 
 
     
     
         12 . The device of  claim 11  wherein the erase gate is separated from the second cell terminal by an erase gate dielectric. 
     
     
         13 . A device comprising:
 a substrate having an array region in which memory cells are disposed;   a plurality of storage gates of the memory cells disposed in the array region, wherein each of the storage gates comprises a floating gate and a control gate formed over the floating gate and a storage gate dielectric layer disposed in between the floating and control gates; and   a guard ring surrounding the array region, wherein the guard ring is a storage gate guard ring which includes the same layers with the same thickness as the storage gates of the memory cells.   
     
     
         14 . The device of  claim 13  wherein the guard ring comprises a width which is uniform throughout all four sides of the guard ring. 
     
     
         15 . The device of  claim 13  wherein:
 the floating gate comprises a floating gate dielectric layer on the substrate and a floating gate electrode layer on the floating gate dielectric layer; 
 the control gate comprises a control gate electrode layer; and 
 the storage gate dielectric layer is disposed in between the floating and control gate electrode layers. 
 
     
     
         16 . The device of  claim 13  wherein the storage gate includes a hard mask layer and dielectric spacers which are spacer stacks disposed on sidewalls of the storage gate. 
     
     
         17 . The device of  claim 13  comprising:
 first and second cell terminals which are adjacent to first and second sides of the storage gates, wherein the second cell terminals of adjacent storage gates form a common second cell terminal; and 
 access gates disposed adjacent to the first memory cell terminals and erase gates disposed over the common second cell terminals of the memory cells. 
 
     
     
         18 . The device of  claim 17  wherein the erase gate is separated from the second cell terminal by an erase gate dielectric. 
     
     
         19 . The device of  claim 17  wherein top surfaces of the access, erase and control gates are substantially coplanar. 
     
     
         20 . A device comprising:
 a substrate having an array region in which memory cells are disposed and a logic region in which logic devices are disposed;   a plurality of storage gates of the memory cells disposed in the array region, wherein each of the storage gates comprises a floating gate and a control gate formed over the floating gate, and wherein
 the floating gate comprises a floating gate dielectric layer on the substrate, a floating gate electrode layer on the floating gate dielectric layer, and a storage gate dielectric layer disposed in between the floating and control gates; and 
   a guard ring surrounding the array region, wherein the guard ring is a storage gate guard ring having the same layers as the storage gates of the memory cells, wherein the guard ring is displaced away from edge regions of the array region.