Semiconductor package

Abstract

A semiconductor device is disclosed. The semiconductor device comprises a die, a redistribution structure, and a plurality of metal posts. The redistribution structure comprises a first sublayer, a second sublayer, and a third sublayer. The first sublayer comprises a plurality of first metal traces with a first trace thickness A. The third sublayer comprises a plurality of third metal traces with a third trace thickness C. The first trace thickness A is smaller than the third trace thickness C.

1 . A semiconductor device, comprising:
 a die, the die having an active surface, the die comprising a plurality of metal pads on the active surface;   a redistribution structure, the redistribution structure comprising a first sublayer, a second sublayer, and a third sublayer, the second sublayer being located between the first sublayer and the third sublayer, the first sublayer comprising a plurality of first vias and a plurality of first metal traces, the first vias being cup-shaped, the first metal traces having a first trace thickness A, the second sublayer comprising a plurality of second vias and a plurality of second metal traces, the second vias being cup-shaped, the second metal traces having a second trace thickness B, the third sublayer comprising a plurality of third vias and a plurality of third metal traces, the third vias being cup-shaped, the third metal traces having a third trace thickness C; and   a plurality of metal posts, the first vias being in contact with the metal posts, the metal pads being in contact with the metal posts;   wherein the first trace thickness A is smaller than the third trace thickness C.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the semiconductor device comprises a plurality of metal pillars, the metal pillars are beside the die, and the metal pillars are connected to the redistribution structure. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the redistribution structure is a first redistribution structure, and the semiconductor device further comprises a second redistribution structure, and a second die, the second die being a memory die, the second die being connected to the second redistribution structure, the second redistribution structure being connected to the metal pillars. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a third width ratio of at least one of the third vias is smaller than a first width ratio of at least one of the first vias. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a height of the metal posts is between 1 micrometer and 5 micrometer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a molding material is filled between the the first sublayer and the active surface of the die. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first sublayer comprises polyimide. 
     
     
         8 . A semiconductor device, comprising:
 a die, the die having an active surface, the die comprising a plurality of metal pads on the active surface;   a redistribution structure, the redistribution structure comprising a first sublayer, a second sublayer, a third sublayer, and a fourth sublayer, the second sublayer being located between the first sublayer and the third sublayer, the third sublayer being located between the second sublayer and the fourth sublayer, the first sublayer comprising a plurality of first vias and a plurality of first metal traces, the first vias being cup-shaped, the first metal traces having a first trace thickness A, the second sublayer comprising a plurality of second vias and a plurality of second metal traces, the second vias being cup-shaped, the second metal traces having a second trace thickness B, the third sublayer comprising a plurality of third vias and a plurality of third metal traces, the third vias being cup-shaped, the third metal traces having a third trace thickness C, the fourth sublayer comprising a plurality of fourth vias and a plurality of fourth metal traces, the fourth metal vias being cup-shaped, the fourth metal traces having a fourth trace thickness D; and   a plurality of metal posts, the first vias being in contact with the metal posts, the metal pads being in contact with the metal posts;   wherein the first trace thickness A is smaller than the fourth trace thickness D.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the semiconductor device comprises a plurality of metal pillars, the metal pillars are beside the die, and the metal pillars are connected to the redistribution structure. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the redistribution structure is a first redistribution structure, and the semiconductor device further comprises a second redistribution structure, and a second die, the second die being a memory die, the second die being connected to the second redistribution structure, the second redistribution structure being connected to the metal pillars. 
     
     
         11 . The semiconductor device of  claim 8 , wherein a fourth width ratio of at least one of the fourth vias is smaller than a second width ratio of at least one of the second vias. 
     
     
         12 . The semiconductor device of  claim 8 , wherein a height of the metal posts is between 1 micrometer and 5 micrometer. 
     
     
         13 . The semiconductor device of  claim 8 , wherein a molding material is filled between the the first sublayer and the active surface of the die. 
     
     
         14 . The semiconductor device of  claim 8 , wherein the first sublayer comprises polyimide. 
     
     
         15 . A semiconductor device, comprising:
 a die, the die having an active surface the die comprising a plurality of metal pads on the active surface;   a redistribution structure, the redistribution structure comprising a first sublayer, a second sublayer, and a third sublayer, the second sublayer being located between the first sublayer and the third sublayer, the first sublayer comprising a plurality of first vias and a plurality of first metal traces, the first metal traces having a first trace thickness A, the second sublayer comprising a plurality of second vias and a plurality of second metal traces, the second metal traces having a second trace thickness B, the third sublayer comprising a plurality of third vias and a plurality of third metal traces, the third metal traces having a third trace thickness C; and   a plurality of metal posts, the first vias being in contact with the metal posts, the metal pads being in contact with the metal posts; and   a molding material filled between the first sublayer and the active surface of the die;   wherein a trace thickness ratio (C/A) between the third trace thickness C and the first trace thickness A is greater than 1 and smaller than 10.   
     
     
         16 . The semiconductor device of  claim 15 , wherein a third width ratio of at least one of the third vias is smaller than a first width ratio of at least one of the first vias. 
     
     
         17 . The semiconductor device of  claim 15 , wherein a minimum pitch of the first vias is smaller than a minimum pitch of the third vias. 
     
     
         18 . The semiconductor device of  claim 15 , the semiconductor device further comprises an adhesive layer on the die. 
     
     
         19 . The semiconductor device of  claim 18 , wherein the molding material is in contact with at least one lateral side of the adhesive layer. 
     
     
         20 . The semiconductor device of  claim 18 , wherein the molding material does not cover a top side of the adhesive layer. 
     
     
         21 . A semiconductor device, comprising:
 a die, the die having an active surface, the die comprising a plurality of metal pads on the active surface;   a redistribution structure, the redistribution structure comprising a first sublayer, a second sublayer, and a third sublayer, the second sublayer being located between the first sublayer and the third sublayer, the first sublayer comprising a plurality of first vias and a plurality of first metal traces, the first vias being cup-shaped, the second sublayer comprising a plurality of second vias and a plurality of second metal traces, the second vias being cup-shaped, the third sublayer comprising a plurality of third vias and a plurality of third metal traces, the third vias being cup-shaped; and   a plurality of metal posts, the first vias being in contact with the metal posts, the metal pads being in contact with the metal posts;   wherein a third width ratio of at least one of the third vias is smaller than a first width ratio of at least one of the first vias.