Semiconductor device and method of fabricating the same

Abstract

A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed at a first side of the active fins. A second device isolation layer is disposed at a second side of the active fins. A top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side. A normal gate extends across the active fins in a second direction crossing the first direction. A first dummy gate extends across the active fins and the first device isolation layer in the second direction. A second dummy gate extends across the second device isolation layer in the second direction.

1 . A semiconductor device comprising:
 a plurality of active fins protruding from a substrate and extending in a first direction;   a first device isolation layer disposed at a first side of the active fins;   a second device isolation layer disposed at a second side of the active fins, wherein a top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side;   a normal gate extending across the active fins in a second direction crossing the first direction;   a first dummy gate extending across the active fins and the first device isolation layer in the second direction; and   a second dummy gate extending across the second device isolation layer in the second direction.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a bottom surface of the second device isolation layer is lower than a bottom surface of the first device isolation layer. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the bottom surface of the second device isolation layer is lower than a top surface of the substrate. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the second dummy gate is distant from the first side of the active fins. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second dummy gate overlaps the second device isolation layer and at least one of the active fins. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 an impurity epitaxial layer disposed on the active fins and between the first dummy gate and the normal gate adjacent to the first dummy gate.   
     
     
         7 . The semiconductor device of  claim 1 , wherein each of the normal gate, the first dummy gate and the second dummy gate includes a metal gate. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the normal gate includes a metal gate and at least one of the first dummy gate and the second dummy gate includes a poly Si gate. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a third dummy gate extending across the first device isolation layer in the second direction and being spaced apart from the first side of the active fins.   
     
     
         10 . The semiconductor device of  claim 9 , wherein each of the normal gate and the first to third dummy gates includes a metal gate. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the normal gate includes a metal gate and at least one of the first to third dummy gates includes a poly Si gate. 
     
     
         12 . A semiconductor device comprising:
 a first active fin protruding from a substrate and extending in a first direction;   a second active fin protruding from the substrate and extending in the first direction, wherein the second active fin is spaced apart from the first active fin in a second direction crossing the first direction;   a first device isolation layer disposed at a first side of the first active fin and at a first side of the second active fin;   a second device isolation layer disposed at a second side of the first active fin and at a second side of the second active fin, wherein the second side of the first active fin is opposite to the first side of the first active fin;   a first dummy gate extending in the second direction and overlapping the first active fin, the second active fin and the first device isolation layer; and   a second dummy gate extending in the second direction and overlapping the first active fin and the second device isolation layer.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the second dummy gate overlaps a portion of the second active fin. 
     
     
         14 . The semiconductor device of  claim 12 , further comprising:
 a third dummy gate extending across the first device isolation layer in the second direction and being spaced apart from the first active fin and the second active fin.   
     
     
         15 . The semiconductor device of  claim 12 , further comprising:
 a normal gate extending across the first and second active fins in the second direction, wherein the normal gate includes a metal gate and at least one of the first dummy gate and the second dummy gate includes a poly Si gate.   
     
     
         16 . The semiconductor device of  claim 12 , wherein a top surface of the second device isolation layer is higher than a top surface of the first device isolation layer. 
     
     
         17 . The semiconductor device of  claim 16 , wherein a bottom surface of the second device isolation layer is lower than a bottom surface of the first device isolation layer. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the bottom surface of the second device isolation layer is lower than a top surface of the substrate. 
     
     
         19 .- 23 . (canceled) 
     
     
         24 . A semiconductor device comprising:
 a plurality of active fins protruding from a substrate and extending in a first direction;   a device isolation layer disposed at one side of the active fins and extended in a second direction crossing the first direction;   a normal gate extending across the active fins in a second direction crossing the first direction;   a first dummy gate extending across the device isolation layer in the second direction; and   a second dummy gate extending across the active fins and the device isolation layer in the second direction.   
     
     
         25 . (canceled) 
     
     
         26 . The semiconductor device of  claim 24 , wherein the normal gate includes a metal gate and at least one of the first dummy gate and the second dummy gate includes a poly Si gate. 
     
     
         27 .- 42 . (canceled)