Method for fabricating semiconductor device

Abstract

In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor device, comprising:
 forming a first active region and a second active region;   forming a gate electrode intersecting the first active region and the second active region on the first active region and the second active region;   conformally forming a conductive buffer layer on the first active region, the second active region, and the gate electrode;   forming a first mask pattern covering the first active region on the buffer layer; and   performing a halo ion implantation process in the second active region at sides of the gate electrode using the first mask pattern.   
     
     
         2 . The method of  claim 1 , further comprising:
 after removing the first mask pattern, forming a second mask pattern which covers the second active region on the buffer layer; and   performing the halo ion implantation process on the first active region at sides of the gate electrode using the second mask pattern.   
     
     
         3 . The method of  claim 1 , wherein the first mask pattern is a BARC 
     
     
         4 . The method of  claim 1 , wherein the buffer layer includes a TiN film or an amorphous silicon film. 
     
     
         5 . The method of  claim 1 , wherein the first active region is a region where a pull-up transistor of an SRAM is formed and the second active region is a region where a pull-down transistor of the SRAM is formed. 
     
     
         6 . The method of  claim 1 , wherein the first active region and the second active region are fin type active patterns. 
     
     
         7 . A method for fabricating a semiconductor device, comprising:
 forming a first fin type active pattern and a second fin type active pattern on a substrate, the first fin type active pattern and the second fin type active pattern being formed in a first region and a second region of the substrate, respectively;   forming a first dummy gate electrode intersecting the first fin type active pattern on the first fin type active pattern and a second dummy gate electrode intersecting the second fin type active pattern on the second fin type active pattern;   forming a buffer layer including a TiN film or amorphous silicon on the first and second fin type active patterns and the first and second dummy gate electrodes;   forming a first mask pattern covering the first region on the buffer layer, the first mask pattern comprising a BARC;   forming a first impurity region in the second fin type active pattern at sides of the second dummy gate electrode using the first mask pattern as a mask of an ion implantation process;   after removing the first mask pattern, forming a second mask pattern covering the second region on the buffer layer, the second mask pattern being a BARC; and   forming a second impurity region having a different conductive type from the first impurity region, in the first fin type active pattern at sides of the first dummy gate electrode using the second mask pattern as a mask of an ion implantation process.   
     
     
         8 . The method of  claim 7 , wherein the first impurity region and the second impurity region comprises halo ion implantation regions. 
     
     
         9 . The method of  claim 7 , further comprising:
 sequentially removing the second mask pattern and the buffer layer;   forming a first source/drain at sides of the first dummy gate electrode; and   forming a second source/drain at sides of the second dummy gate electrode.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming an interlayer insulating layer which covers the first and second dummy gate electrodes and the first and second sources/drains, on the substrate;   planarizing the interlayer insulating layer to expose the first dummy gate electrode and the second dummy gate electrode;   removing the first dummy gate electrode and the second dummy gate electrode to form a first trench and a second trench in the interlayer insulating layer; and   forming a first gate electrode which buries the first trench and a second gate electrode which buries the second trench.