Methodology Of Incorporating Wafer Physical Measurement With Digital Simulation For Improving Semiconductor Device Fabrication

Abstract

A hot spot methodology incorporates wafer physical measurement with digital simulation for identifying and monitoring critical hot spots. Wafer physical data are collected from the processed wafer of the semiconductor device on a plurality of target locations. Hot spot candidates and corresponding simulation data are generated by digital simulation based on models and verifications of optical proximity and lithographic process correction according to the design data of a semiconductor device. Data analytics provides data correlation between the collected wafer physical data and the simulation data. Data analytics further performs data correction on the simulation data according to the wafer physical data that have best correlation with the simulation data to better predict critical hot spots.

What is claimed is: 
     
         1 . A method of incorporating wafer physical measurement with digital simulation for identifying critical hot spots in manufacturing a semiconductor device, comprising the steps of:
 collecting a plurality of physical data from a plurality of locations on a processed wafer of a semiconductor device;   generating a plurality of simulation data of a plurality of hot spot candidates based on digital simulation according to chip design data of the semiconductor device; and   determining a plurality of critical hot spots by performing data analytics based on the physical data and the simulation data;   wherein the data analytics in the step of determining critical hot spots includes data correlation between the physical data and the simulation data, and data correction of the simulation data according to the physical data that are most correlated with the simulation data.   
     
     
         2 . The method as claimed in  claim 1 , wherein the step of collecting a plurality of physical data includes:
 preparing a plurality of critical dimension targets on the plurality of locations according to the chip design data of the semiconductor device; and   measuring critical dimension data of the plurality of critical dimension targets on the processed wafer.   
     
     
         3 . The method as claimed in  claim 2 , wherein the step of generating a plurality of simulation data of hot spot candidates includes predicting edge placement error data by the digital simulation and selecting the hot spot candidates according to the predicted edge placement error data, and the data analytics in the step of determining a plurality of critical hot spots is accomplished by data correlation between the measured critical dimension data and the predicted edge placement error data, and data correction of the predicted edge placement error data is based on the measured critical dimension data that are most correlated with the predicted edge placement error data. 
     
     
         4 . The method as claimed in  claim 3 , wherein the data correlation between the measured critical dimension data and the predicted edge placement error data is based on location proximity, and the data correction of the predicted edge placement error data is accomplished by calibrating the predicted edge placement error data according to the measured critical dimension data of the critical dimension targets whose locations have closest proximity with the locations corresponding to the predicted edge placement error data. 
     
     
         5 . The method as claimed in  claim 3 , wherein determining a plurality of critical hot spots by performing data analytics further incorporates design clips extracted from the chip design data for the critical dimension targets and locations corresponding to the predicted edge placement error data. 
     
     
         6 . The method as claimed in  claim 5 , wherein the data correlation between the measured critical dimension data and the predicted edge placement error data is based on design clips and the data correction of the predicted edge placement error data is accomplished by calibrating the predicted edge placement error data according to the measured critical dimension data of the critical dimension targets whose design clips have best correlation with the design clips corresponding to the predicted edge placement error data. 
     
     
         7 . The method as claimed in  claim 6 , wherein the data correlation based on design clips is performed by correlating design features extracted from the design clips. 
     
     
         8 . The method as claimed in  claim 6 , wherein the data correlation based on design clips is performed by correlating simulated images modelled and rendered from the design clips. 
     
     
         9 . The method as claimed in  claim 6 , wherein the data correlation based on design clips is performed by correlating image characteristics extracted from simulated images modelled and rendered from the design clips. 
     
     
         10 . The method as claimed in  claim 6 , wherein the design clips of the critical dimension targets and the design clips corresponding to the predicted edge placement error data include the design clips of at least one layer underneath a current layer of the semiconductor device. 
     
     
         11 . The method as claimed in  claim 6 , wherein the design clips of the critical dimension targets include the design clips of a predetermined size of neighborhood of the locations of the critical dimension targets, and the design clips corresponding to the predicted edge placement error data include the design clips of a predetermined size of neighborhood of the locations corresponding to the predicted edge placement error data. 
     
     
         12 . The method as claimed in  claim 3 , wherein the step of collecting a plurality of physical data further includes collecting physical images in a predetermined size of neighborhood of the locations of the critical dimension targets, and the data correlation between the measured critical dimension data and the predicted edge placement error data is based on correlating the physical images of the critical dimension targets with simulated images modelled and rendered from design clips extracted from the chip design data corresponding to the predicted edge placement error data. 
     
     
         13 . The method as claimed in  claim 12 , wherein correlating the physical images with the simulated images is accomplished by correlating design features extracted from the physical images or the simulated images. 
     
     
         14 . The method as claimed in  claim 12 , wherein correlating the physical images with the simulated images is accomplished by correlating polygon characteristics extracted from the physical images or the simulated images. 
     
     
         15 . The method as claimed in  claim 12 , wherein correlating the physical images with the simulated images is accomplished by correlating image characteristics extracted from the physical images or the simulated images. 
     
     
         16 . A method of identifying and monitoring critical hot spots in manufacturing a semiconductor device, comprising the steps of:
 collecting a plurality of physical data from a plurality of locations on a processed wafer of a semiconductor device;   generating a plurality of simulation data of a plurality of hot spot candidates based on digital simulation according to chip design data of the semiconductor device;   determining a plurality of critical hot spots by performing data analytics based on the physical data and the simulation data; and   inspecting the plurality of critical hot spots on the processed wafer of the semiconductor device;   wherein the data analytics in the step of determining critical hot spots includes data correlation between the physical data and the simulation data, and data correction of the simulation data according to the physical data that are most correlated with the simulation data.   
     
     
         17 . The method as claimed in  claim 16 , wherein the step of collecting a plurality of physical data includes:
 preparing a plurality of critical dimension targets on the plurality of locations according to the chip design data of the semiconductor device; and   measuring critical dimension data of the plurality of critical dimension targets on the processed wafer.   
     
     
         18 . The method as claimed in  claim 17 , wherein the step of generating a plurality of simulation data of hot spot candidates includes predicting edge placement error data by the digital simulation and selecting the hot spot candidates according to the predicted edge placement error data, and the data analytics in the step of determining a plurality of critical hot spots is accomplished by data correlation between the measured critical dimension data and the predicted edge placement error data, and data correction of the predicted edge placement error data is based on the measured critical dimension data that are most correlated with the predicted edge placement error data. 
     
     
         19 . The method as claimed in  claim 18 , wherein the step of determining a plurality of critical hot spots is executed in-line along with the step of measuring critical dimension data to dynamically determine the plurality of critical hot spots for inspection and monitoring while critical dimension data measurement is ongoing on a same processed wafer. 
     
     
         20 . The method as claimed in  claim 16 , wherein the step of inspecting the plurality of critical hot spots and the step of collecting a plurality of physical data are performed on a same wafer process monitoring tool without unloading the processed wafer. 
     
     
         21 . The method as claimed in  claim 16 , wherein the physical data collected from the plurality of locations on the processed wafer and results of inspecting the plurality of critical hot spots are fed back for tuning model and recipe of optical proximity correction for the chip design data. 
     
     
         22 . The method as claimed in  claim 16 , wherein the physical data collected from the plurality of locations on the processed wafer and results of inspecting the plurality of critical hot spots are fed back for tuning design for manufacture model and recipe in lithographic process of manufacturing the semiconductor device.