Semiconductor devices and methods of fabricating the same

Abstract

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

1 - 19 . (canceled) 
     
     
         20 . A semiconductor device comprising:
 a substrate comprising a top surface extending horizontally;   a first gate structure and a second gate structure on the substrate;   an isolation layer in the substrate;   a first trench in the substrate and between the first gate structure and the second gate structure, the first trench comprising a first side corner, a second side corner, and a bottom corner, the first side corner protruding toward a first channel region under the first gate structure, the second side corner protruding toward a second channel region under the second gate structure, and the bottom corner protruding downward into the substrate;   a second trench in the substrate and between the second gate structure and the isolation layer, the second trench comprising a third side corner and a side portion opposing the third side corner, the third side corner protruding toward the second channel region under the second gate structure, and the side portion exposing a sidewall of the isolation layer;   a first epitaxial layer in the first trench; and   a second epitaxial layer in the second trench,   wherein a top surface of the second epitaxial layer extends toward the isolation layer from an interface of the second epitaxial layer with the second gate structure, and   wherein at least a portion of the top surface of the second epitaxial layer is slanted downward with respect to the top surface of the substrate.   
     
     
         21 . The semiconductor device of  claim 20 ,
 wherein the second gate structure further comprises a spacer, and   wherein the spacer of the second gate structure contacts the top surface of the second epitaxial layer.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the first trench comprises an undercut cavity extending laterally beneath the spacer of the second gate structure. 
     
     
         23 . The semiconductor device of  claim 20 , wherein a top surface of the first epitaxial layer extends substantially parallel with respect to the top surface of the substrate. 
     
     
         24 . The semiconductor device of  claim 20 , wherein the first gate structure and the second gate structure respectively comprise a gate electrode. 
     
     
         25 . The semiconductor device of  claim 20 , wherein the first gate structure and the second gate structure respectively comprise a gate insulating layer, a gate electrode, and a gate capping pattern. 
     
     
         26 . The semiconductor device of  claim 20 , wherein at least a portion of the bottom corner of the first trench is substantially flat. 
     
     
         27 . The semiconductor device of  claim 20 , wherein at least a portion of the bottom corner of the first trench is substantially rounded. 
     
     
         28 . The semiconductor device of  claim 20 , further comprising a silicide layer on a top surface of the first epitaxial layer, and between the first gate structure and the second gate structure. 
     
     
         29 . The semiconductor device of  claim 28 , wherein the silicide layer is not lower than the top surface of the substrate. 
     
     
         30 . The semiconductor device of  claim 20 , further comprising a silicide layer on the top surface of the second epitaxial layer, and between the second gate structure and the isolation layer. 
     
     
         31 . The semiconductor device of  claim 30 , wherein at least a portion of the top surface of the silicide layer is slanted downward with respect to the top surface of the substrate. 
     
     
         32 . The semiconductor device of  claim 30 , wherein at least a portion of the silicide layer is lower than the top surface of the substrate. 
     
     
         33 . The semiconductor device of  claim 20 , wherein at least a portion of the second epitaxial layer contacts the sidewall of the isolation layer that is exposed by the side portion of the second trench. 
     
     
         34 . The semiconductor device of  claim 20 , wherein the first epitaxial layer comprises a layer with a different lattice constant from the substrate. 
     
     
         35 . The semiconductor device of  claim 34 , wherein the first epitaxial layer comprises an epitaxially-grown silicon germanium (SiGe) layer. 
     
     
         36 . A semiconductor device comprising:
 a substrate comprising a top surface extending horizontally;   a first gate structure and a second gate structure on the substrate, each of the first gate structure and the second gate structure comprising a spacer;   an isolation layer in the substrate;   a first trench in the substrate, and between the first gate structure and the second gate structure, the first trench comprising two side corners and a bottom corner, the two side corners of the first trench respectively protruding toward a channel region under one of the first gate structure and the second gate structure, and the bottom corner of the first trench protruding downward into the substrate;   a second trench in the substrate and between the second gate structure and the isolation layer, the second trench comprising a side corner and a side portion opposing the side corner of the second trench, the side corner of the second trench protruding toward a channel region under the second gate structure, the side portion of the second trench exposing a sidewall of the isolation layer;   a first epitaxial layer in the first trench; and   a second epitaxial layer in the second trench,   wherein a top surface of the second epitaxial layer extends toward the isolation layer from an interface of the second epitaxial layer with the second gate structure, and   wherein at least a portion of the top surface of the second epitaxial layer is slanted downward with respect to the top surface of the substrate.   
     
     
         37 . The semiconductor device of  claim 36 , wherein the spacer of the second gate structure contacts the top surface of the second epitaxial layer. 
     
     
         38 . The semiconductor device of  claim 36 , wherein the first trench comprises an undercut cavity extending laterally beneath the spacer of the second gate structure. 
     
     
         39 . The semiconductor device of  claim 36 , wherein a top surface of the first epitaxial layer extends substantially parallel with respect to the top surface of the substrate. 
     
     
         40 . The semiconductor device of  claim 36 , wherein the first gate structure and the second gate structure respectively comprise a gate electrode. 
     
     
         41 . The semiconductor device of  claim 36 , wherein the first gate structure and the second gate structure respectively comprise a gate insulating layer, a gate electrode, and a gate capping pattern. 
     
     
         42 . The semiconductor device of  claim 36 , wherein at least a portion of the bottom corner of the first trench is substantially flat. 
     
     
         43 . The semiconductor device of  claim 36 , wherein at least a portion of the bottom corner of the first trench is substantially rounded. 
     
     
         44 . The semiconductor device of  claim 36 , further comprising a silicide layer on a top surface of the first epitaxial layer, and between the first gate structure and the second gate structure. 
     
     
         45 . The semiconductor device of  claim 44 , wherein the silicide layer is not lower than the top surface of the substrate. 
     
     
         46 . The semiconductor device of  claim 36 , further comprising a silicide layer on the top surface of the second epitaxial layer, and between the second gate structure and the isolation layer. 
     
     
         47 . The semiconductor device of  claim 46 , wherein at least a portion of the top surface of the silicide layer is slanted downward with respect to the top surface of the substrate. 
     
     
         48 . The semiconductor device of  claim 46 , wherein at least a portion of the silicide layer is lower than the top surface of the substrate. 
     
     
         49 . The semiconductor device of  claim 36 , wherein at least a portion of the second epitaxial layer contacts the sidewall of the isolation layer that is exposed by the side portion of the second trench.