Circuit design system and semiconductor circuit designed by using the system

Abstract

A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

1 .- 15 . (canceled) 
     
     
         16 . A semiconductor circuit comprising:
 a first transistor P 1  gated to a voltage level of a second node Z 2  and supplying a power supply voltage to a first node Z 1 ;   a second transistor P 2  connected in parallel to the first transistor P 1 , gated to a voltage level of the first node Z 1  and supplying the power supply voltage to the second node Z 2 ;   a third transistor N 3  gated to a voltage level of an input signal and supplying a ground voltage;   a fourth transistor N 1  connected in series to the third transistor N 3 , gated to the power supply voltage and transferring an output of the third transistor N 3  to the first node Z 1 ;   a fifth transistor N 4  gated to an inverted voltage level of the input signal and supplying the ground voltage; and   a sixth transistor N 2  connected in series to the fifth transistor N 4 , gated to the power supply voltage and transferring an output of the fifth transistor N 4  to the second node Z 2 ,   wherein the third transistor N 3  and the fifth transistor N 4  include a high-k dielectric layer.   
     
     
         17 . The semiconductor circuit of  claim 16 , wherein drain-gate voltages of the third transistor N 3  and the fifth transistor N 4  operating in an accumulation mode are higher than drain-gate voltages of the fourth transistor N 1  and the sixth transistor N 2  operating in the accumulation mode. 
     
     
         18 . The semiconductor circuit of  claim 16 , wherein thicknesses of the gate insulating films of the third transistor N 3  and the fifth transistor N 4  are smaller than thicknesses of the gate insulating films of the fourth transistor N 1  and the sixth transistor N 2 . 
     
     
         19 . The semiconductor circuit of  claim 16 , wherein channel lengths of the third transistor N 3  and the fifth transistor N 4  are smaller than channel lengths of the fourth transistor N 1  and the sixth transistor N 2 . 
     
     
         20 . The semiconductor circuit of  claim 16 , wherein the third transistor N 3  is gated to the voltage level of the input signal and pulls down the first node Z 1 , and the second transistor P 2  is gated to the voltage level of the first node Z 1  and pulls up the second node Z 2 . 
     
     
         21 . The semiconductor circuit of  claim 20 , wherein when the voltage level of the input signal is a first voltage level, the third transistor N 3  and the fourth transistor N 1  are turned on, and the voltage level of the first node Z 1  is a second voltage level different from the first voltage level. 
     
     
         22 . The semiconductor circuit of  claim 20 , wherein when the voltage level of the input signal is a first voltage level, the second transistor P 2  is turned on. 
     
     
         23 . The semiconductor circuit of  claim 16 , wherein the fifth transistor N 4  is gated to the voltage level of the input signal and pulls down the second node Z 2 , and the first transistor P 1  is gated to the voltage level of the second node Z 2  and pulls up the first node Z 1 . 
     
     
         24 . The semiconductor circuit of  claim 23 , wherein when the voltage level of the input signal is a second voltage level, the fifth transistor N 4  and the sixth transistor N 2  are turned on, and the voltage level of the second node Z 2  is the second voltage level. 
     
     
         25 . The semiconductor circuit of  claim 23 , wherein when the voltage level of the input signal is a first voltage level, the first transistor P 1  is turned on. 
     
     
         26 . A semiconductor circuit comprising:
 a first transistor P 1  gated to a voltage level of a second node Z 2  and supplying a power supply voltage to a first node Z 1 ;   a second transistor P 2  connected in parallel to the first transistor P 1 , gated to a voltage level of the first node Z 1  and supplying the power supply voltage to the second node Z 2 ;   a third transistor N 3  gated to a voltage level of an input signal and supplying a ground voltage;   a fourth transistor N 1  connected in series to the third transistor N 3 , gated to the power supply voltage and transferring an output of the third transistor N 3  to the first node Z 1 ;   a fifth transistor N 4  gated to an inverted voltage level of the input signal and supplying the ground voltage; and   a sixth transistor N 2  connected in series to the fifth transistor N 4 , gated to the power supply voltage and transferring an output of the fifth transistor N 4  to the second node Z 2 ,   wherein an area of the third transistor N 3  is smaller than an area of the fourth transistor N 1 , and an area of the fifth transistor N 4  is smaller than an area of the sixth transistor N 2 .   
     
     
         27 . The semiconductor circuit of  claim 26 , wherein drain-gate voltages of the third transistor N 3  and the fifth transistor N 4  operating in an accumulation mode are higher than drain-gate voltages of the fourth transistor N 1  and the sixth transistor N 2  operating in the accumulation mode. 
     
     
         28 . The semiconductor circuit of  claim 26 , wherein thicknesses of the gate insulating films of the third transistor N 3  and the fifth transistor N 4  are smaller than thicknesses of the gate insulating films of the fourth transistor N 1  and the sixth transistor N 2 . 
     
     
         29 . The semiconductor circuit of  claim 26 , wherein channel lengths of the third transistor N 3  and the fifth transistor N 4  are smaller than channel lengths of the fourth transistor N 1  and the sixth transistor N 2 . 
     
     
         30 . The semiconductor circuit of  claim 26 , wherein threshold voltages of the third transistor N 3  and the fifth transistor N 4  are lower than threshold voltages of the fourth transistor N 1  and the sixth transistor N 2 . 
     
     
         31 . A semiconductor circuit comprising:
 a second transistor P 2  gated to a voltage level of the first node Z 1  and supplying the power supply voltage to the output node;   a third transistor N 3  gated to a voltage level of an input signal and supplying a ground voltage; and   a fourth transistor N 1  connected in series to the third transistor N 3 , gated to the power supply voltage and transferring an output of the third transistor N 3  to the first node Z 1 ;   wherein the voltage level of the input signal is shifted to the voltage level of the power supply voltage provided by the second transistor P 2  which is turned on, and   wherein a thickness of the gate insulating film of the third transistor N 3  is smaller than a thickness of the gate insulating film of the fourth transistor N 1 .   
     
     
         32 . The semiconductor circuit of  claim 31 , wherein a drain-gate voltage of the third transistor N 3  operating in an accumulation mode is higher than a drain-gate voltage of the fourth transistor N 1  operating in the accumulation mode. 
     
     
         33 . The semiconductor circuit of  claim 31 , wherein a channel length of the third transistor N 3  is smaller than a channel length of the fourth transistor N 1 . 
     
     
         34 . The semiconductor circuit of  claim 31 , wherein a threshold voltage of the third transistor N 3  is lower than a threshold voltage of the fourth transistor N 1 . 
     
     
         35 . The semiconductor circuit of  claim 31 , wherein an area of the third transistor N 3  is smaller than an area of the fourth transistor N 1 . 
     
     
         36 .- 40 . (canceled)