Embedded resilient buffer

Abstract

Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

We claim: 
     
         1 . An apparatus comprising:
 a first sequential unit;   a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input;   a compare unit to receive an output from the first sequential unit; and   a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.   
     
     
         2 . The apparatus of  claim 1  further comprises:
 a second sequential unit to receive output of the compare unit, the output of the second sequential unit to generate a rollback signal for adjusting a read pointer for another queue or the first EDS. 
 
     
     
         3 . The apparatus of  claim 1  further comprises:
 a read pointer logic to offset read operation of the first queue from write operation to the first queue by one or more clock cycles. 
 
     
     
         4 . The apparatus of  claim 1  further comprises a second queue to receive output of the compare unit. 
     
     
         5 . The apparatus of  claim 1 , wherein the second queue is a 1-bit first-in/first-out (FIFO) queue to store error history. 
     
     
         6 . The apparatus of  claim 1 , wherein the first and second queues are at least one of:
 first-in/first-out (FIFO);   shift-register; or   serial chain of SRAM cells.   
     
     
         7 . The apparatus of  claim 1  further comprises:
 a second selection unit to receive the outputs of each storage unit of the first queue, the second selection unit controllable by a read pointer. 
 
     
     
         8 . The apparatus of  claim 1  further comprises:
 a logic unit to receive output of the second selection unit and output of a storage unit of the second queue, the output of the storage unit of the second queue selected using the read pointer, the logic unit to generate an output indicating validity of data read from the first queue. 
 
     
     
         9 . The apparatus of  claim 1 , wherein the first queue comprises at least three storage units. 
     
     
         10 . The apparatus of  claim 1 , wherein the first sequential unit is operable to double sample the first input.