Layout structure of heterojunction bipolar transistors

Abstract

A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.

What is claimed is: 
     
         1 . A layout structure of heterojunction bipolar transistors (HBTs), comprising:
 one or more HBTs formed on a substrate, each comprising a base electrode, an emitter electrode, and a collector electrode;   a passive layer formed on the HBTs, comprising an emitter pad and a collector pad, wherein the emitter pad is electrically connected to each of the one or more emitter electrodes, and the collector pad is electrically connected to each of the one or more collector electrodes;   a first dielectric layer covering on the passive layer, comprising one or more emitter via holes formed on the emitter pad through the first dielectric layer and one or more collector via holes formed on the collector pad through the first dielectric layer;   a collector redistribution layer formed on the first dielectric layer and extending into the one or more collector via holes to form an electrical connection to the collector pad;   one or more emitter copper pillars, each disposed on at least one of the one or more emitter via holes and filling therein to form an electrical connection to the emitter pad; and   one or more collector copper pillars, each disposed on the collector redistribution layer to form an electrical connection to the collector redistribution layer,   wherein the collector pad forms a collector pad extension region in the passive layer, at least one of the one or more collector via holes is formed on the collector pad extension region, and each of the one or more collector copper pillars is disposed on at least one of the one or more collector via holes on the collector pad extension region and fills therein, and wherein each of the more emitter copper pillars fills at least one of the one or more emitter via holes to reduce the difference in height between the one or more emitter copper pillars and the one or more collector copper pillars.   
     
     
         2 . The layout structure of HBTs according to  claim 1 , wherein an emitter redistribution layer is included on the first dielectric layer and extending into at least one of the one or more emitter via holes below one of the one or more emitter copper pillars and forms an electrical connection to the emitter pad. 
     
     
         3 . The layout structure of HBTs according to  claim 2 , wherein one or more capacitors and resistors are included coupling to the HBTs, and the one or more capacitors and resistors are disposed in the passive layer near the emitter pad excluding the region between the emitter pad and the collector pad. 
     
     
         4 . The layout structure of HBTs according to  claim 2 , wherein one or more capacitors and resistors are included coupling to the HBTs, and the one or more capacitors and resistors are disposed in the passive layer under at least one of the one or more emitter copper pillars near the emitter pad excluding the region between the emitter pad and the collector pad. 
     
     
         5 . The layout structure of HBTs according to  claim 2 , wherein the substrate is made of compound semiconductor material GaAs, GaN, SiC, or sapphire. 
     
     
         6 . The layout structure of HBTs according to  claim 1 , wherein one or more capacitors and resistors are included coupling to the HBTs, and the one or more capacitors and resistors are disposed in the passive layer near the emitter pad excluding the region between the emitter pad and the collector pad. 
     
     
         7 . The layout structure of HBTs according to  claim 1 , wherein one or more capacitors and resistors are included coupling to the HBTs, and the one or more capacitors and resistors are disposed in the passive layer under at least one of the one or more emitter copper pillars near the emitter pad excluding the region between the emitter pad and the collector pad. 
     
     
         8 . The layout structure of HBTs according to  claim 1 , wherein the substrate is made of compound semiconductor material GaAs, GaN, SiC, or sapphire.