Trench semiconductor device layout configurations

Abstract

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

1 . A trench semiconductor device comprising:
 a layer of semiconductor material;   an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material; and   an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of first interior trench portions and a plurality of second interior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of first interior trench portions being arranged perpendicular to the plurality of second interior trench portions with each of the plurality of first interior trench portions being connected to at least one of the plurality of second interior trench portions.   
     
     
         2 . The trench semiconductor device of  claim 1 , wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a snake pattern. 
     
     
         3 . The trench semiconductor device of  claim 2 , further comprising a plurality of intermediate trench portions between the exterior trench pattern and the interior trench pattern, the plurality of intermediate trench portions at least partially surrounding the interior trench pattern. 
     
     
         4 . The trench semiconductor device of  claim 2 , wherein the exterior trench pattern is formed with the plurality of exterior trench portions separated from one another by gaps therebetween. 
     
     
         5 . The trench semiconductor device of  claim 2 , wherein the exterior trench pattern is formed with at least one notch feature located adjacent to openings between legs of the snake pattern formed by the plurality of first interior trench portions and the plurality of second interior trench portions. 
     
     
         6 . The trench semiconductor device of  claim 1 , wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a plurality of separated closed rectangles. 
     
     
         7 . The trench semiconductor device of  claim 1 , wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a pattern having an outer frame and a plurality of vertical trench legs connecting top and bottom horizontal segments of the outer frame. 
     
     
         8 . The trench semiconductor device of  claim 1 , wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form a grid pattern. 
     
     
         9 . The trench semiconductor device of  claim 8 , wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form the grid pattern with the plurality of first interior trench portions including extensions that extend beyond an outer rectangular perimeter of the grid pattern. 
     
     
         10 . The trench semiconductor device of  claim 8 , wherein the plurality of first interior trench portions and the plurality of second interior trench portions are connected to each other to form the grid pattern with an offset such successive columns of horizontal legs of the grid pattern formed by the plurality of second interior trench portions connecting adjacent vertical legs of the grid pattern formed by the plurality of first interior trench portions are offset from one another. 
     
     
         11 . A trench semiconductor device comprising:
 a layer of semiconductor material;   an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material; and   an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material, arranged at angles to each other and connected to each other to form a plurality of six sided polygons.   
     
     
         12 . The trench semiconductor device of  claim 11 , wherein the six sided polygons are arranged in a honeycomb pattern. 
     
     
         13 . The trench semiconductor device of  claim 11 , wherein the plurality of interior trench portions are arranged at angles to each other and connected to each other to form a geometric pattern including plurality of six sided polygons and at least one eight sided polygon. 
     
     
         14 . A trench semiconductor device comprising:
 a layer of semiconductor material;   an exterior trench pattern formed in the layer of semiconductor material, the exterior trench pattern including a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of exterior trench portions being formed as a plurality of separated exterior trench segments; and   an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern, the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material, the plurality of interior trench portions being formed as a plurality of parallel vertical trench legs.