Multiport memory cell having improved density area

Abstract

A multiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

We claim: 
     
         1 . A memory cell, comprising:
 a data storing component comprising a plurality of load transistors;   a first memory access component coupled to the data storing component;   a second memory access component coupled to the data storing component;   a plurality of lines coupled to the first memory access component and the second memory access component; and   a read/write assist transistor coupled to the plurality of load transistors of the data storing component, wherein the plurality of load transistors is configured to prevent a change in a state of the data storing component until the read/write assist transistor is deactivated.   
     
     
         2 . The memory cell of  claim 1 , wherein the plurality of load transistors is configured to allow activation of a transfer gate to allow single ended read operations. 
     
     
         3 . The memory cell of  claim 1 , wherein the read/write assist transistor is configured to be activated for the duration of a read operation and during write operations, the read/write assist transistor is configured to be activated to impress a desired voltage level before or after deactivation of one or more memory access components that are activated as a part of the write operation. 
     
     
         4 . The memory cell of  claim 1 , wherein the plurality of lines comprise:
 first and second bit lines coupled to the first memory access component; first and second bit lines coupled to the second memory access component;   first and second write lines coupled to the first memory access component; and   first and second write lines coupled to the second memory access component.   
     
     
         5 . The memory cell of  claim 4 , wherein the memory cell is configured for a differential write, wherein either the first and second write lines coupled to the first memory access component or the first and second write lines coupled to the second memory access component are activated. 
     
     
         6 . The memory cell of  claim 4 , wherein the memory cell is configured for a single ended write operation, wherein a single write line and a single transistor of one of the first memory access component and the second memory access component is activated. 
     
     
         7 . The memory cell of  claim 1 , wherein the read/write assist transistor is coupled to terminals of the plurality of load transistors of the memory cell. 
     
     
         8 . The memory cell of  claim 1 , wherein the read/write assist transistor is located inside the memory cell. 
     
     
         9 . The memory cell of  claim 1 , wherein the memory access components are coupled to respective internal nodes of the memory cell. 
     
     
         10 . The memory cell of  claim 1 , wherein the memory cell comprises nodes that are coupled to true and complement voltage levels. 
     
     
         11 . A processor, comprising:
 a CPU;   a memory component coupled to the CPU, wherein the memory component comprises a memory cell comprising:
 a data storing component comprising a plurality of load transistors; 
 a first memory access component coupled to a first side of the data storing component; 
 a second memory access component coupled to a second side of the data storing component; 
 a plurality of lines coupled to the first memory access component and the second memory access component; and 
 a read/write assist transistor coupled to the plurality of load transistors of the data storing component, wherein the plurality of load transistors is sized to prevent a change in a state of the data storing component until the read/write assist transistor is deactivated. 
   
     
     
         12 . The memory cell of  claim 11 , wherein the plurality of load transistors is sized to allow activation of a transfer gate to allow single ended read operations. 
     
     
         13 . The memory cell of  claim 11 , wherein the memory component is selected from the group consisting of a register and a cache memory. 
     
     
         14 . The memory cell of  claim 11 , wherein the read/write assist transistor is configured to be activated for the duration of a read operation and during write operations the read/write assist transistor is configured to be activated to impress a desired voltage level before or after deactivation of one or more memory access components that are activated as a part of the write operation. 
     
     
         15 . The processor of  claim 11 , wherein the plurality of lines of the memory cell comprises:
 first and second bit lines coupled to the first memory access component;   first and second bit lines coupled to the second memory access component;   first and second write lines coupled to the first memory access component; and   first and second write lines coupled to the second memory access component.   
     
     
         16 . The processor of  claim 15 , wherein the memory cell is configured for a differential write, wherein either the first and second write lines coupled to the first memory access component of the first and second write lines coupled to the second memory access component are activated. 
     
     
         17 . The processor of  claim 15 , wherein the memory cell is configured for a single ended write operation, wherein a single write line and a single transistor of one of the first memory access component and the second memory access component is activated. 
     
     
         18 . A method for accessing a memory cell, comprising:
 in a mode comprising write operation:
 biasing one or more bit lines to either a high or low voltage state; 
 placing a high voltage level onto the gate of a memory access component; 
 turning a read/write assist transistor on to impress the desired voltage level after the memory access component is turned off. 
   
     
     
         19 . The method of  claim 18  comprising executing a differential write wherein either first and second write lines coupled to a first memory access component or first and second write lines coupled to a second memory access component are activated. 
     
     
         20 . The method of  claim 18  comprising executing a single ended write operation wherein a single write line and a single transistor of one of a first memory access component and a second memory access component is activated.