Assignee
SOFT MACHINES INC
US·9 granted patents·16 pending applications·48 citations·filing 2011–2017
Top patents by PatentIndex Score
25 records- 0197US9053292B2Processor executing super instruction matrix with register file configurable for single or multiple threads operationsSOFT MACHINES INC·Filed 2012·Granted Jun 9, 2015·36 cites·17 claims
- 0288US9575762B2Method for populating register view data structure by using register template snapshotsSOFT MACHINES INC·Filed 2014·Granted Feb 21, 2017·9 cites·18 claims
- 0374US9501280B2Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to referSOFT MACHINES INC·Filed 2014·Granted Nov 22, 2016·2 cites·17 claims
- 0464US9361227B2Systems and methods for faster read after write forwarding using a virtual addressSOFT MACHINES INC·Filed 2013·Granted Jun 7, 2016·1 cites·18 claims
- 0556US9436476B2Method and apparatus for sorting elements in hardware structuresSOFT MACHINES INC·Filed 2013·Granted Sep 6, 2016·0 cites·24 claims
- 0656US2017024212A1Hardware acceleration components for translating guest instructions to native instructionsSOFT MACHINES INC·Filed 2016·Application pending·0 cites
- 0755US9569216B2Method for populating a source view data structure by using register template snapshotsSOFT MACHINES INC·Filed 2014·Granted Feb 14, 2017·0 cites·18 claims
- 0855US9454491B2Systems and methods for accessing a unified translation lookaside bufferSOFT MACHINES INC·Filed 2015·Granted Sep 27, 2016·0 cites·24 claims
- 0955US2017123807A1Method for emulating a guest centralized flag architecture by using a native distributed flag architectureSOFT MACHINES INC·Filed 2017·Application pending·0 cites
- 1054US2014281116A1Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address BitsSOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 1154US2015046683A1Method for using register templates to track interdependencies among blocks of instructionsSOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 1254US2015046686A1Method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templatesSOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 1353US9348754B2Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcherSOFT MACHINES INC·Filed 2012·Granted May 24, 2016·0 cites·19 claims
- 1451US9582322B2Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remappingSOFT MACHINES INC·Filed 2013·Granted Feb 28, 2017·0 cites·20 claims
- 1551US2017123993A1Systems and methods for read request bypassing a last level cache that interfaces with an external fabricSOFT MACHINES INC·Filed 2017·Application pending·0 cites
- 1649US2015039859A1Microprocessor accelerated code optimizerSOFT MACHINES INC·Filed 2011·Application pending·0 cites
- 1749US2016041930A1Systems and methods for supporting a plurality of load accesses of a cache in a single cycleSOFT MACHINES INC·Filed 2015·Application pending·0 cites
- 1848US2015095588A1Lock-based and synch-based method for out of order loads in a memory consistency model using shared memory resourcesSOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 1948US2015205605A1Load store buffer agnostic to threads implementing forwarding from different threads based on store senioritySOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 2048US2015095591A1Method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cacheSOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 2148US2015100734A1Semaphore method and system with out of order loads in a memory consistency model that constitutes loads reading from memory in orderSOFT MACHINES INC·Filed 2014·Application pending·0 cites
- 2242US2014344554A1Microprocessor accelerated code optimizer and dependency reordering methodSOFT MACHINES INC·Filed 2011·Application pending·0 cites
- 2341US2016260475A1Multiport memory cell having improved density areaSOFT MACHINES INC·Filed 2016·Application pending·0 cites
- 2437US2016026484A1System converter that executes a just in time optimizer for executing code from a guest imageSOFT MACHINES INC·Filed 2015·Application pending·0 cites
- 2537US2016026486A1An allocation and issue stage for reordering a microinstruction sequence into an optimized microinstruction sequence to implement an instruction set agnostic runtime architectureSOFT MACHINES INC·Filed 2015·Application pending·0 cites
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