Microprocessor accelerated code optimizer

Abstract

A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

What is claimed is: 
     
         1 . In a microprocessor, a method for accelerating code optimization, comprising:
 fetching an incoming microinstruction sequence using an instruction fetch component;   transferring the fetched macro instructions to a decoding component for decoding into microinstructions;   performing optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;   outputting the optimized microinstruction sequence to a microprocessor pipeline for execution; and   storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.   
     
     
         2 . The method of  claim 1 , wherein a copy of the decoded microinstructions are stored in a microinstruction cache. 
     
     
         3 . The method of  claim 1 , wherein the optimization processing is performed using an allocation and issue stage of the microprocessor. 
     
     
         4 . The method of  claim 3 , wherein the allocation and issue stage further comprises an instruction scheduling and optimizer component that reorders the microinstruction sequence into the optimized micro instruction sequence. 
     
     
         5 . The method of  claim 1 , wherein the optimization processing further comprises dynamically unrolling microinstruction sequences. 
     
     
         6 . The method of  claim 1 , wherein the optimization processing is implemented through a plurality of iterations. 
     
     
         7 . The method of  claim 1 , wherein the optimization processing is implemented through a register renaming process to enable the reordering. 
     
     
         8 . A microprocessor, comprising:
 an instruction fetch component for fetching an incoming microinstruction sequence;   a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence;   an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;   a microprocessor pipeline coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence; and   a sequence cache coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence.   
     
     
         9 . The microprocessor of  claim 8 , wherein a copy of the decoded microinstructions are stored in a microinstruction cache. 
     
     
         10 . The microprocessor of  claim 8 , wherein the optimization processing is performed using an allocation and issue stage of the microprocessor. 
     
     
         11 . The microprocessor of  claim 10 , wherein the allocation and issue stage further comprises an instruction scheduling and optimizer component that reorders the microinstruction sequence into the optimized micro instruction sequence. 
     
     
         12 . The microprocessor of  claim 8 , wherein the optimization processing further comprises dynamically unrolling microinstruction sequences. 
     
     
         13 . The microprocessor of  claim 8 , wherein the optimization processing is implemented through a plurality of iterations. 
     
     
         14 . The microprocessor of  claim 8 , wherein the optimization processing is implemented through a register renaming process to enable the reordering. 
     
     
         15 . In a microprocessor, a method for accelerating code optimization, comprising:
 accessing an input microinstruction sequence by using a software-based optimizer instantiated in memory;   using SIMD instructions to populate a dependency matrix with dependency information extracted from the input microinstruction sequence;   scanning a plurality of rows of the dependency matrix to perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;   outputting the optimized microinstruction sequence to a microprocessor pipeline for execution; and   storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.   
     
     
         16 . The method of  claim 15 , wherein optimization processing further includes scanning the plurality of rows of the dependency matrix to identify matching instructions. 
     
     
         17 . The method of  claim 16 , wherein optimization processing further includes analyzing the matching instructions to determine whether the matching instructions comprise a blocking dependency, and wherein renaming is performed to remove the blocking dependency. 
     
     
         18 . The method of  claim 17 , wherein instructions corresponding to first matches of each row of the dependency matrix are moved into a corresponding dependency group. 
     
     
         19 . The method of  claim 15 , wherein copies of the optimized microinstruction sequences are stored in a memory hierarchy of the microprocessor. 
     
     
         20 . The method of  claim 19 , wherein the memory hierarchy comprises an L1 cache and an L2 cache. 
     
     
         21 . The method of  claim 20 , wherein the memory hierarchy for further comprises a system memory. 
     
     
         22 . A microprocessor, comprising:
 an instruction fetch component for fetching an incoming microinstruction sequence;   a decoding component coupled to the instruction fetch component to receive the fetched macro instruction sequence and decode into a microinstruction sequence;   an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups;   a microprocessor pipeline coupled to the allocation and issue stage to receive and execute the optimized microinstruction sequence;   a sequence cache coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence; and   a hardware component for moving instructions in the incoming microinstruction sequence.   
     
     
         23 . The microprocessor of  claim 22 , wherein at least one register is renamed and at least one instruction is moved ahead of the branch without inserting compensation code. 
     
     
         24 . The microprocessor of  claim 23 , wherein the hardware component keeps track of whether a branch biased decision is true, and wherein in case of a wrongly predicted branch, the hardware component automatically rolls back state in order to execute a correct instruction sequence. 
     
     
         25 . The microprocessor of  claim 24 , wherein the hardware component jumps to original code in memory to execute the correct instruction sequence in case of a wrongly predicted branch. 
     
     
         26 . The microprocessor of  claim 25  wherein the harder component causes a flushing of a miss predicted instruction sequence in the case of a wrongly predicted branch.