Systems and methods for supporting a plurality of load accesses of a cache in a single cycle

Abstract

A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory.

What is claimed is: 
     
         1 . A method for accessing a data cache, comprising:
 receiving a plurality of requests to access the data cache, wherein the data cache comprises a plurality of blocks;   responsive to the plurality of requests to access the data cache, accessing a tag memory comprising a plurality of copies of tags for each entry in the data cache and identifying tags associated with each request of the plurality of requests; and   accessing the data cache based on the tags associated with each request of the plurality of requests, wherein two or more requests of the plurality of requests associated with access a same block of the plurality of blocks are arbitrated during the identifying of tags associated with each request of the plurality of requests.   
     
     
         2 . The method of  claim 1 , wherein the arbitration of the two or more requests is performed during the same clock cycle as the accessing of the tag memory. 
     
     
         3 . The method of  claim 1 , wherein the accessing of the data cache based on the tags comprises a plurality of loads from the data cache performed in a single clock cycle.  
     
     
         4 . The method of  claim 1 , wherein each request of the plurality of requests to access the data cache is associated with a respective copy of tags that correspond to entries in the data cache. 
     
     
         5 . The method of  claim 1 , wherein the two or more requests of the plurality of requests to access a same block of the plurality of blocks request access to different addresses within the same block of the data cache. 
     
     
         6 . The method of  claim 1 , wherein the plurality of blocks comprise respective portions of a level one data cache. 
     
     
         7 . The method of  claim 1 , wherein the tag memory comprises a tag Static Random-Access Memory (SRAM). 
     
     
         8 . An apparatus comprising:
 a data cache comprising a plurality of data blocks;   a tag memory configured to maintain a plurality of copies of tags that correspond to entries of the data cache; and   a cache subsystem configured to access the tag memory and the data cache, wherein the cache subsystem is configured to perform arbitration in a same clock cycle as a plurality of accesses of the tag memory.    
     
     
         9 . The apparatus of  claim 8 , wherein the cache subsystem is configured to perform the arbitration in response to a plurality of requests to a block of the plurality of data blocks. 
     
     
         10 . The apparatus of  claim 8 , wherein accessing of the data cache based on the tags comprises a plurality of loads from the data cache performed in a single clock cycle. 
     
     
         11 . The apparatus of  claim 8 , wherein the plurality of data blocks are configured for a plurality of loads operations to be executed within a single clock cycle. 
     
     
         12 . The apparatus of  claim 8 , wherein each request of a plurality of requests is associated with a respective copy of tags that correspond to cache line entries of the data cache. 
     
     
         13 . The apparatus of  claim 8 , wherein the data cache is divided into four eight kilobyte data blocks. 
     
     
         14 . The apparatus of  claim 8 , wherein the arbitration is performed in response to a plurality of requests to access the same block at different addresses in the same cycle.  
     
     
         15 . The apparatus of  claim 8 , wherein the tag memory comprises a tag Static Random-Access Memory (SRAM). 
     
     
         16 . A processor comprising:
 a cache system, comprising:
 a data cache comprising a plurality of blocks; 
 a tag memory configured to store tags that correspond to entries of the data cache; and 
 a cache controller configured for processing a plurality of requests to the data cache, comprising:
 a request receiving component for receiving the plurality of requests to access the data cache; 
 a tag memory component configured to identify tags that are associated with respective requests of the plurality of requests; and 
 a data cache accessing component for accessing the data cache based on the tags that are associated with the respective requests, wherein the cache controller is configured to perform arbitration based on two or more requests of the plurality of requests requesting access to a block of the plurality of blocks in a same clock cycle as the accessing of the tag memory. 
 
   
     
     
         17 . The processor of  claim 15 , wherein the tag memory component is configured for accessing a tag memory comprising a plurality of copies of tags for each entry in the data cache.  
     
     
         18 . The processor of  claim 15 , wherein the accessing of the data cache comprises a plurality of loads that are executed within a single clock cycle. 
     
     
         19 . The processor of  claim 15 , wherein the arbitration of the two or more requests is performed during the same clock cycle as identifying tags associated with the plurality of requests. 
     
     
         20 . The processor of  claim 15 , wherein each request of the plurality of requests to access the data cache is associated with a respective copy of tags that correspond to entries in the data cache.