Systems and methods for read request bypassing a last level cache that interfaces with an external fabric

Abstract

Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to said read transaction, and wherein said read transaction is canceled if said read transaction is a hit in said last level cache or does not access said last level cache.

We claim: 
     
         1 . A method for read request bypassing a last level cache which interfaces with an external fabric, comprising:
 accessing a read request for a read transaction;   generating a phantom read transaction identifier for said read transaction; and   forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to said read transaction, and wherein said read transaction is canceled if said read transaction is a hit in said last level cache or does not access said last level cache.   
     
     
         2 . The method of  claim 1 , wherein said phantom read transaction identifier is converted to a pointer to a real read transaction identifier if said read transaction is a miss in said last level cache. 
     
     
         3 . The method of  claim 1  wherein said phantom read transaction identifier comprises a bit set to differentiate said phantom read transaction identifier from said read transaction identifier. 
     
     
         4 . The method of  claim 1  wherein for a 32 entry load queue said phantom read transaction identifier is associated with one bit of six bits. 
     
     
         5 . The method of  claim 1  wherein said phantom read transaction identifier is supplied from said last level cache. 
     
     
         6 . The method of  claim 1  wherein said phantom read transaction identifier acts as a pointer to said read transaction identifier. 
     
     
         7 . The method of  claim 1  wherein said read transaction identifier is a pointer to a read queue in said last level cache. 
     
     
         8 . A cache controller, comprising:
 an accessor for accessing a read request for a read transaction;   a generator for generating a phantom read transaction identifier for said read transaction; and   a forwarder for forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to said read transaction, and wherein said read transaction is canceled if said read transaction is a hit in said last level cache or does not access said last level cache.   
     
     
         9 . The cache controller of  claim 8  wherein said phantom read transaction identifier is converted to a pointer to a real read transaction identifier if said read transaction is a miss in said last level cache. 
     
     
         10 . The cache controller of  claim 8  wherein said phantom read transaction identifier comprises a bit set to differentiate said phantom read transaction identifier from said read transaction identifier. 
     
     
         11 . The cache controller of  claim 8  wherein for a 32 entry load queue said phantom read transaction identifier is one bit of six bits. 
     
     
         12 . The cache controller of  claim 8  wherein said phantom read transaction identifier is supplied from said last level cache. 
     
     
         13 . The cache controller of  claim 8  wherein said phantom read transaction identifier acts as a pointer to said read transaction identifier. 
     
     
         14 . The cache controller of  claim 8  wherein said read transaction identifier is a pointer to a read queue in said last level cache. 
     
     
         15 . A processor, comprising:
 a CPU;   a cache system; and   a cache controller, wherein said cache controller comprises:   an accessor for accessing a read request for a read transaction;   a generator for generating a phantom read transaction identifier for said read transaction; and   a forwarder for forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to said read transaction, and wherein said read transaction is canceled if said read transaction is a hit in said last level cache or does not access said last level cache.   
     
     
         16 . The processor of  claim 15  wherein said phantom read transaction identifier is converted to a pointer to a real read transaction identifier if said read transaction is a miss in said last level cache. 
     
     
         17 . The processor of  claim 15  wherein said phantom read transaction identifier comprises a bit set to differentiate said phantom read transaction identifier from said read transaction identifier. 
     
     
         18 . The processor of  claim 15  wherein for a 32 entry load queue said phantom read transaction identifier is one bit of six bits. 
     
     
         19 . The processor of  claim 15  wherein said phantom read transaction identifier is supplied from said last level cache. 
     
     
         20 . The processor of  claim 15  wherein said phantom read transaction identifier acts as a pointer to said read transaction identifier.