Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits

Abstract

A microprocessor implemented method for processing a load instruction is disclosed. The method comprises computing a virtual address corresponding to the load instruction. Next, it comprises performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel using early calculated lower address bits of the virtual address. Subsequently, it comprises retrieving a set of entries from the TLB corresponding to a first group of lower address bits transmitted to the TLB, wherein the set of entries comprise a plurality of virtual addresses and corresponding physical addresses. Further, it comprises finding a matching entry for the virtual address in the set of entries using upper bits of the virtual address, wherein the matching entry comprises a physical address corresponding to the virtual address. Finally, it comprises finding a matching entry in the data cache memory using the physical address.

What is claimed is: 
     
         1 . A microprocessor implemented method for processing a load instruction, said method comprising:
 initiating a computation of a virtual address corresponding to said load instruction;   performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel responsive to and using early calculated lower address bits of said virtual address;   retrieving a set of entries from said TLB corresponding to a first group of lower address bits transmitted to said TLB, wherein said set of entries comprise a plurality of virtual addresses and corresponding physical addresses;   finding a matching entry for said virtual address in said set of entries responsive to and using upper bits of said virtual address, wherein said matching entry comprises a physical address corresponding to said virtual address, and wherein said upper bits are available subsequent to said lower address bits; and   finding a matching entry in said data cache memory using said physical address.   
     
     
         2 . The method of  claim 1 , further comprising:
 routing said lower address bits to said TLB and said data cache memory using a higher metal route relative to other bits of said virtual address.   
     
     
         3 . The method of  claim 1 , wherein said finding a matching entry in said data cache further comprises:
 retrieving a set of entries from said data cache memory corresponding to a second group of lower address bits transmitted to said data cache memory, wherein said entries comprise a plurality of physical addresses and corresponding cache data; and   comparing a plurality of tag bits associated with said physical address to said plurality of physical addresses to find said matching entry in said data cache memory.   
     
     
         4 . The method of  claim 1 , wherein said performing and said initiating are performed in a same cycle. 
     
     
         5 . The method of  claim 1 , wherein said physical address is routed through a one-hot multiplexer to perform a lookup in said data cache memory. 
     
     
         6 . The method of  claim 1 , further comprising:
 transmitting said lower address bits of said virtual address to a load store queue (LSQ) in a same cycle as said computing; and   performing a partial match in said LSQ using said lower address bits to find a prior aliasing store, wherein said prior aliasing store stores to a same address as said load instruction.   
     
     
         7 . The method of  claim 6 , further comprising:
 performing a prediction that said load instruction has a prior aliasing store in said LSQ; and   responsive to a determination that there is no partial match in said LSQ and no prediction is available, retrieving data corresponding to said load instruction from said data cache memory.   
     
     
         8 . The method of  claim 7 , further comprising:
 responsive to a determination that there is a partial match in said LSQ or that said prediction indicates a prior aliasing store, waiting for said virtual address to fully compute in order to perform a look-up in said LSQ.   
     
     
         9 . A processor unit configured to perform a method for processing a load instruction, said method comprising:
 initiating a computation of a virtual address corresponding to said load instruction;   performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel responsive to and using early calculated lower address bits of said virtual address;   retrieving a set of entries from said TLB corresponding to a first group of lower address bits transmitted to said TLB, wherein said set of entries comprise a plurality of virtual addresses and corresponding physical addresses;   finding a matching entry for said virtual address in said set of entries responsive to and using upper bits of said virtual address, wherein said matching entry comprises a physical address corresponding to said virtual address, and wherein said upper bits are available subsequent to said lower address bits; and   finding a matching entry in said data cache memory using said physical address.   
     
     
         10 . The processor unit of  claim 9 , wherein said method further comprises:
 routing said lower address bits to said TLB and said data cache memory using a higher metal route relative to other bits of said virtual address.   
     
     
         11 . The processor unit of  claim 9 , wherein said finding a matching entry in said data cache further comprises:
 retrieving a set of entries from said data cache memory corresponding to a second group of lower address bits transmitted to said data cache memory, wherein said entries comprise a plurality of physical addresses and corresponding cache data; and   comparing a plurality of tag bits associated with said physical address to said plurality of physical addresses to find said matching entry in said data cache memory.   
     
     
         12 . The processor unit of  claim 9 , wherein said performing and said initiating are performed in a same cycle. 
     
     
         13 . The processor unit of  claim 9 , wherein said physical address is routed through a one-hot multiplexer to perform a lookup in said data cache memory. 
     
     
         14 . The processor unit of  claim 9 , wherein said method further comprises:
 transmitting said lower address bits of said virtual address to a load store queue (LSQ) in a same cycle as said computing; and   performing a partial match in said LSQ using said lower address bits to find a prior aliasing store, wherein said prior aliasing store stores to a same address as said load instruction.   
     
     
         15 . The processor unit of  claim 14 , wherein said method further comprises:
 performing a prediction that said load instruction has a prior aliasing store in said LSQ; and   responsive to a determination that there is no partial match in said LSQ and no prediction is available, retrieving data corresponding to said load instruction from said data cache memory.   
     
     
         16 . The processor unit of  claim 15 , wherein said method further comprises:
 responsive to a determination that there is a partial match in said LSQ or that said prediction indicates a prior aliasing store, waiting for said virtual address to fully compute in order to perform a look-up in said LSQ.   
     
     
         17 . An apparatus configured to perform a method for processing a load instruction, said apparatus comprising:
 a memory;   a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and further wherein said processor is configured to perform a method, said method comprising:
 initiating a computation of a virtual address corresponding to said load instruction; 
 performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel responsive to and using early calculated lower address bits of said virtual address; 
 retrieving a set of entries from said TLB corresponding to a first group of lower address bits transmitted to said TLB, wherein said set of entries comprise a plurality of virtual addresses and corresponding physical addresses; 
 finding a matching entry for said virtual address in said set of entries responsive to and using upper bits of said virtual address, wherein said matching entry comprises a physical address corresponding to said virtual address, and wherein said upper bits are available subsequent to said lower address bits; and 
 finding a matching entry in said data cache memory using said physical address. 
   
     
     
         18 . The apparatus of  claim 17 , wherein said method further comprises:
 routing said lower address bits to said TLB and said data cache memory using a higher metal route relative to other bits of said virtual address.   
     
     
         19 . The apparatus of  claim 17 , wherein said finding a matching entry in said data cache further comprises:
 retrieving a set of entries from said data cache memory corresponding to a second group of lower address bits transmitted to said data cache memory, wherein said entries comprise a plurality of physical addresses and corresponding cache data; and   comparing a plurality of tag bits associated with said physical address to said plurality of physical addresses to find said matching entry in said data cache memory.   
     
     
         20 . The apparatus of  claim 17 , wherein said performing and said initiating are performed in a same cycle. 
     
     
         21 . A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ), said method comprising:
 initiating a computation of a virtual address corresponding to said load instruction;   transmitting early calculated lower address bits of said virtual address to a load store queue (LSQ) in a same cycle as said initiating; and   performing a partial match in said LSQ responsive to and using said lower address bits to find a prior aliasing store, wherein said prior aliasing store stores to a same address as said load instruction.   
     
     
         22 . The method of  claim 21  further comprising:
 performing a prediction that said load instruction has a prior aliasing store in said LSQ; and 
 responsive to a determination that there is no partial match in said LSQ and no prediction is available, retrieving data corresponding to said load instruction from said data cache memory. 
 
     
     
         23 . The method of  claim 22  further comprising:
 responsive to a determination that there is a partial match in said LSQ or that said prediction indicates a prior aliasing store, waiting for said virtual address to fully compute in order to perform a look-up in said LSQ.