Reduced Variation MOSFET Using a Drain-Extension-Last Process

Abstract

A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

What is claimed is: 
     
         1 . A method of forming a metal-oxide semiconductor (MOS) transistor comprising:
 forming sidewall spacers on two opposite sides of a gate of the MOS transistor, the sidewall spacers formed over an oxide layer;   implanting and annealing a source implant and drain implant of the MOS transistor;   enhancing the oxide layer thickness over the source implant and drain implant;   sacrificing the sidewall spacers;   clearing the oxide layer exposed after the sacrificing of the sidewall spacers;   creating a first recess where the oxide layer has been cleared on the heavy source implant side;   creating a second recess where the oxide layer has been cleared on the heavy drain implant side;   filling the first recess with a conductive material; and   filling the second recess with the conductive material.   
     
     
         2 . The method of  claim 1 , wherein the first recess extends from partially within the source implant to a transistor channel extending under the gate. 
     
     
         3 . The method of  claim 1 , wherein the second recess extends from partially within the drain implant to a transistor channel extending under the gate. 
     
     
         4 . The method of  claim 1 , wherein the conductive material filling any one of the first recess and the second recess is an epitaxial material consisting of any one of: epitaxial silicon, epitaxial silicon:germanium, epitaxial germanium or epitaxial silicon:carbon. 
     
     
         5 . The method of  claim 1 , wherein filling the first recess and/or the second recess with the conductive material comprises:
 depositing an epitaxial material.   
     
     
         6 . The method of  claim 5 , further comprising:
 processing at least an interface between a channel of the transistor formed under at least the gate and the conductive material in the first recesses and the conductive material in the second recess to be free of variations associated with thermally induced diffusion or migration.   
     
     
         7 . The method of  claim 5 , wherein depositing the epitaxial material further comprises:
 incorporating either n-type dopants (donors) or p-type dopants (acceptors) during the epitaxial deposition process.   
     
     
         8 . The method of  claim 5 , wherein depositing the epitaxial material further comprises:
 implanting either n-type dopants (donors) or p-type dopants (acceptors) subsequent to the epitaxial deposition process.   
     
     
         9 . The method of  claim 8 , wherein activation of the implanted dopants further comprises a dedicated annealing step. 
     
     
         10 . The method of  claim 8 , wherein activation of the implanted dopants further comprises an annealing step associated with metal silicide processing. 
     
     
         11 . The method of  claim 1 , wherein the conductive filling material is any one of: a metal or a metallic compound. 
     
     
         12 . A method of forming a metal-oxide semiconductor (MOS) transistor formed on a semiconductor substrate, the method comprising:
 forming a source extension connecting a source of the metal-oxide semiconductor to a channel under a gate structure of the metal oxide semiconductor by selectively depositing and filling a first recess formed in the semiconductor substrate between the source and the gate structure and forming a drain extension connecting a drain of the metal-oxide semiconductor to the channel under a gate structure of the metal oxide semiconductor by selectively depositing and filling a second recess formed between the drain and the gate structure, using a conductive material, where in the selectively depositing of the conductive material is done at a temperature not exceeding 650 degrees Celsius.   
     
     
         13 . The method of  claim 12 , wherein the conductive material is a semiconducting material. 
     
     
         14 . The method of  claim 12  wherein the selective deposition of conductive material is done by selective epitaxial deposition. 
     
     
         15 . The method of  claim 14 , wherein the material deposited by selective epitaxy is any of: epitaxial silicon, epitaxial silicon:germanium, epitaxial germanium or epitaxial silicon:carbon. 
     
     
         16 . The method of  claim 12 , wherein the semiconductor substrate is any one of: a silicon substrate or a silicon-on-insulator (SOI) substrate. 
     
     
         17 . The method of  claim 12 , wherein the use of temperatures not exceeding 650 degrees Celsius reduce diffusion of dopants into the semiconductor substrate and under the gate of the MOS transistor. 
     
     
         18 . A method of forming a metal-oxide semiconductor (MOS) transistor formed on a semiconductor substrate, the method comprising:
 forming a source extension connecting a source of the metal-oxide semiconductor to a channel under a gate structure of the metal oxide semiconductor by selectively depositing and filling a first recess formed in the semiconductor substrate between the source region and the gate structure, and forming a drain extension connecting a drain of the metal-oxide semiconductor to the channel under a gate structure of the metal oxide semiconductor by selectively depositing and filling a second recess formed between the drain region and the gate structure, using an undoped epitaxial material and doping the undoped epitaxial material to a conductive state by an implantation of selected dopant types, followed by an anneal, where in the selectively depositing of the epitaxial material and annealing of the epitaxial material is done at a temperature not exceeding 650 degrees Celsius.   
     
     
         19 . The method of  claim 18 , wherein the selected dopant type is P-type for a P-channel MOS transistor and the selected dopant is N-type for an N-channel MOS transistor. 
     
     
         20 . The method of  claim 18 , wherein the use of temperatures not exceeding 650 degrees Celsius reduce diffusion of dopants into the semiconductor substrate and under the gate of the MOS transistor. 
     
     
         21 . A method of forming a metal-oxide semiconductor (MOS) transistor comprising:
 forming sidewall spacers on two opposite sides of a gate of the MOS transistor, the sidewall spacers formed over an oxide layer;   implanting and annealing a source implant and a drain implant of the MOS transistor;   sacrificing the sidewall spacers;   clearing the oxide layer exposed after the sacrificing of the sidewall spacers;   creating a first recess where the oxide layer has been cleared and extending away from the gate into the source implant;   creating a second recess where the oxide layer has been cleared and extending away from the gate into the drain implant;   filling the first recess with a conductive material; and   filling the second recess with the conductive material.   
     
     
         22 . The method of  claim 21  wherein the annealing the source and drain implants is performed in an oxidizing environment to enhance the oxide layer thickness over the source implant and drain implants.