Semiconductor device with junction termination extension

Abstract

A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.

1 . A semiconductor device comprising:
 a substrate comprising silicon carbide;   a drift layer disposed over the substrate doped with a first dopant type, so as to have a first conductivity type;   an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type, so as to have a second conductivity type; and   a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width w jte  and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction, wherein the width w jte  is less than or equal to a multiple of five (5) times the width of the one-dimensional depletion width (W depl   _   1D ), and wherein a charge tolerance of the semiconductor device is greater than 1.0×10 13  per cm 2 .   
     
     
         2 . The semiconductor device of  claim 1 , wherein the anode region comprises a material disposed atop the drift layer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the effective doping profile of the junction termination extension is a monotonically decreasing function N(x) of the distance x away from the edge of the primary blocking junction. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the monotonically decreasing function N(x) that governs the effective doping profile of the junction termination extension varies as x 1/2 . 
     
     
         5 . The semiconductor device of  claim 3 , wherein the monotonically decreasing function that governs the effective doping profile of the junction termination extension is:
     N ( x )= N   max +( N   min   −N   max )( x/w   jte ) 1/2 ,   wherein N max  is the average dopant concentration at the edge of the primary blocking junction, and wherein N min  is the average dopant concentration at an outer edge of the junction termination extension.   
     
     
         6 . The semiconductor device of  claim 1 , wherein neighboring ones of the discrete doped regions are separated from their nearest neighbors by a spacing in a range of about 0 to about 2.5λ. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the minimum effective doping is no smaller than 15% of the full JTE dose. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the silicon carbide substrate has a n+ conductivity type, wherein the first dopant type is n-type, such that the first conductivity type is n-type, and wherein the second dopant type is p-type, such that the second conductivity type is p-type. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the silicon carbide substrate has a p-type conductivity type, wherein the first dopant type is n-type, such that the first conductivity type is n-type, and wherein the second dopant type is p-type, such that the second conductivity type is p-type. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the silicon carbide substrate has a n+-type conductivity type, wherein the first dopant type is p-type, such that the first conductivity type is p-type, and wherein the second dopant type is n-type, such that the second conductivity type is n-type. 
     
     
         11 . The semiconductor device of  claim 1 , wherein at least a portion of the junction termination extension is formed in the anode region. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the portion of the junction termination extension formed in the anode region physically connects the anode region to the junction termination extension via a same dopant type. 
     
     
         13 . A semiconductor device comprising
 a semiconductor substrate having a first surface and a second surface;   an active region formed on the substrate; and   an edge region surrounding the active region and having a width W edge , wherein the edge region comprises:   a plurality of discrete corner regions having impurities of a second conductivity type; and   a plurality of discrete straight regions having impurities of the second conductivity type, wherein at least one of the straight regions adjoins respective ones of the corner regions, wherein the effective impurity concentration of the second conductivity type decreases along a direction away from an interface between the edge region and the active region, wherein the shape of the corner regions differs from the shape of the straight regions, and wherein the width of the edge region W edge  is less than or equal to a multiple of five (5) times the one dimensional depletion width (W depl   _   1D ).   
     
     
         14 . The semiconductor device of  claim 13 , wherein at least one of the straight regions has a rectangular shape, and wherein at least one of the corner regions has a trapezoidal shape. 
     
     
         15 . The semiconductor device of  claim 13 , wherein at least one of the straight regions is square. 
     
     
         16 . The semiconductor device of  claim 15 , wherein each of the corner regions is trapezoidal. 
     
     
         17 . The semiconductor device of  claim 13 , wherein the edge region has a charge tolerance of at least about 1.0×10 13 /cm 2 . 
     
     
         18 . The semiconductor device of  claim 17 , wherein the charge tolerance suffices to accommodate an interface charge density of at least about 1×10 12 /cm2. 
     
     
         19 . A semiconductor device comprising
 a semiconductor substrate having a first surface and a second surface;   an active device region formed on the substrate comprising a primary blocking junction; and   an edge region adjacent the primary blocking junction having a width W edge , wherein the edge region comprises a plurality of discrete regions having a plurality of impurities of a first conductivity type, wherein an effective impurity concentration of the first conductivity type in the edge region decreases along a direction away from an interface between the primary blocking junction and the edge region, and wherein the width of the edge region W edge  is less than or equal to a multiple of five (5) times the one dimensional depletion width (W depl   _   1D ).   
     
     
         20 . The semiconductor device of  claim 19 , wherein the edge region has a charge tolerance of at least about 1.0×10 13 /cm 2 .