Devices with thinned wafer

Abstract

Methods, apparatuses and devices are described where a main wafer is irreversibly bonded to a carrier wafer and thinned to reduce a thickness of the main wafer, for example down to a thickness of 300 μm or below.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a carrier wafer bonding device configured to irreversibly bond a carrier wafer to a main wafer at a front side of the main wafer,   a thinning device configured to thin the main wafer from a back side thereof, and   a material removal device configured to selectively remove material from the back side of the main wafer, the second material removal device being downstream of the thinning device.   
     
     
         2 . The apparatus of  claim 1 , further comprising a further material removal device upstream of the carrier wafer bonding device, the further material removal device configured to remove material at a front side of the wafer at a location where a hole through the main wafer is to be formed. 
     
     
         3 . The apparatus of  claim 1 , further comprising a filling device configured to fill gaps generated by the material removal of the further material removal device with a filling material. 
     
     
         4 . The apparatus of  claim 1 , wherein the apparatus is configured to manufacture a micro-electro-mechanical system. 
     
     
         5 . A micro-electro-mechanical system, comprising:
 a main wafer with micro-electro-mechanical structures formed therein, a thickness of the main wafer being less than 300 μm, and   a carrier wafer irreversibly bonded to a front side of the main wafer.   
     
     
         6 . The device of  claim 5 , wherein a thickness of the main wafer is less than 100 μm. 
     
     
         7 . The device of  claim 5 , wherein the main wafer comprises at least one of an acceleration sensor or a pressure sensor. 
     
     
         8 . The device of  claim 5 , wherein the carrier wafer comprises a structured glass wafer. 
     
     
         9 . The device of  claim 5 , further comprising:
 an application specific integrated circuit mounted on top of the carrier wafer and the main wafer, and   a package packaging the application specific integrated circuit, the main wafer and the carrier wafer.