US2016337229A1PendingUtilityA1

Network topology for a scalable multiprocessor system

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Assignee: SILICON GRAPHICS INT CORPPriority: Sep 29, 1999Filed: Jul 26, 2016Published: Nov 17, 2016
Est. expirySep 29, 2019(expired)· nominal 20-yr term from priority
G06F 15/17343H04L 45/14H04L 67/1002G06F 15/17381H04L 67/1001G06F 15/17312
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Claims

Abstract

A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A system for routing information in a computing network, the system comprising:
 a plurality of computing clusters; and   a plurality of high speed routers, wherein the plurality of high speed routers include at least four ports, and the plurality of high speed routers connect each respective computing cluster of the plurality of computing clusters with each other respective computing cluster of the plurality of computing clusters such that communications between two respective computing clusters of the plurality of computing clusters do not travel through a third computing cluster.

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