Inventor · disambiguated record
Martin M. Deneroff
Also filed as: DENEROFF MARTIN M
29 granted patents·4 pending applications·1,088 citations·filing 1993–2019
97Inventor score
Files withSILICON GRAPHICS INC19MILLER STEVEN C3SILICON GRAPHICS INTERNAT3DENEROFF MARTIN M2LUCATA CORP2
Top patents by PatentIndex Score
33 records- 0194US6751698B1Multiprocessor node controller circuit and methodSILICON GRAPHICS INC·Filed 1999·Granted Jun 15, 2004·210 cites·31 claims
- 0294US5272664AHigh memory capacity DRAM SIMMSILICON GRAPHICS INC·Filed 1993·Granted Dec 21, 1993·177 cites·47 claims
- 0393US6215686B1Memory system with switching for data isolationSILICON GRAPHICS INC·Filed 1999·Granted Apr 10, 2001·122 cites·19 claims
- 0491US7406086B2Multiprocessor node controller circuit and methodSILICON GRAPHICS INC·Filed 2004·Granted Jul 29, 2008·65 cites·1 claims
- 0590US6115278AMemory system with switching for data isolationSILICON GRAPHICS INC·Filed 1999·Granted Sep 5, 2000·86 cites·4 claims
- 0690US5504874ASystem and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactionsSILICON GRAPHICS INC·Filed 1993·Granted Apr 2, 1996·131 cites·13 claims
- 0784US7881321B2Multiprocessor node controller circuit and methodSILICON GRAPHICS INTERNAT·Filed 2008·Granted Feb 1, 2011·14 cites·18 claims
- 0882US8402225B2Method for performing cache coherency in a computer systemMILLER STEVEN C·Filed 2010·Granted Mar 19, 2013·5 cites·20 claims
- 0982US7802058B1Method for performing cache coherency in a computer systemSILICON GRAPHICS INTERNAT·Filed 2004·Granted Sep 21, 2010·26 cites·17 claims
- 1080US6877030B2Method and system for cache coherence in DSM multiprocessor system without growth of the sharing vectorSILICON GRAPHICS INC·Filed 2002·Granted Apr 5, 2005·28 cites·41 claims
- 1177US6845410B1System and method for a hierarchical system management architecture of a highly scalable computing systemSILICON GRAPHICS INC·Filed 2000·Granted Jan 18, 2005·29 cites·27 claims
- 1271US9612832B2Parallel processing system for computing particle interactionsDE SHAW RES LLC·Filed 2013·Granted Apr 4, 2017·2 cites·37 claims
- 1369US8433816B2Network topology for a scalable multiprocessor systemDENEROFF MARTIN M·Filed 2008·Granted Apr 30, 2013·3 cites·6 claims
- 1466US9514092B2Network topology for a scalable multiprocessor systemDENEROFF MARTIN M·Filed 2013·Granted Dec 6, 2016·1 cites·18 claims
- 1564US9747099B2Parallel computer architecture for computation of particle interactionsSHAW DAVID E·Filed 2012·Granted Aug 29, 2017·1 cites·9 claims
- 1664US7925839B1System and method for performing memory operations in a computing systemSILICON GRAPHICS INTERNAT·Filed 2008·Granted Apr 12, 2011·2 cites·13 claims
- 1761US10853251B2Diadic memory operations and expanded memory frontend operationsLUCATA CORP·Filed 2019·Granted Dec 1, 2020·0 cites·1 claims
- 1861US6516372B1Partitioning a distributed shared memory multiprocessor computer to facilitate selective hardware maintenanceSILICON GRAPHICS INC·Filed 1999·Granted Feb 4, 2003·44 cites·17 claims
- 1958US2016337229A1Network topology for a scalable multiprocessor systemSILICON GRAPHICS INT CORP·Filed 2016·Application pending·0 cites
- 2057US7181589B2System and method for performing address translation in a computer systemSILICON GRAPHICS INC·Filed 2004·Granted Feb 20, 2007·5 cites·17 claims
- 2157US6578115B2Method and apparatus for handling invalidation requests to processors not present in a computer systemSILICON GRAPHICS INC·Filed 2002·Granted Jun 10, 2003·4 cites·20 claims
- 2256US10628310B2Diadic memory operations and expanded memory frontend operationsLUCATA CORP·Filed 2018·Granted Apr 21, 2020·0 cites·7 claims
- 2356US6973559B1Scalable hypercube multiprocessor network for massive parallel processingSILICON GRAPHICS INC·Filed 1999·Granted Dec 6, 2005·19 cites·20 claims
- 2456US5509125ASystem and method for fair arbitration on a multi-domain multiprocessor busSILICON GRAPHICS INC·Filed 1993·Granted Apr 16, 1996·30 cites·14 claims
- 2553US5664151ASystem and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactionsSILICON GRAPHICS INC·Filed 1995·Granted Sep 2, 1997·24 cites·22 claims
- 2652US6829666B1Modular computing architecture having common communication interfaceSILICON GRAPHICS INC·Filed 1999·Granted Dec 7, 2004·30 cites·25 claims
- 2752US2013282988A1Method for Performing Cache Coherency in a Computer SystemMILLER STEVE C·Filed 2013·Application pending·0 cites
- 2852US2013080709A1System and Method for Performing Memory Operations In A Computing SystemMILLER STEVEN C·Filed 2012·Application pending·0 cites
- 2951US8321634B2System and method for performing memory operations in a computing systemMILLER STEVEN C·Filed 2011·Granted Nov 27, 2012·0 cites·22 claims
- 3050US7398359B1System and method for performing memory operations in a computing systemSILICON GRAPHICS INC·Filed 2004·Granted Jul 8, 2008·1 cites·20 claims
- 3150US2006282648A1Network topology for a scalable multiprocessor systemSILICON GRAPHICS INC·Filed 2005·Application pending·0 cites
- 3249US7197589B1System and method for providing access to a busSILICON GRAPHICS INC·Filed 1999·Granted Mar 27, 2007·22 cites·18 claims
- 3336US6339812B1Method and apparatus for handling invalidation requests to processors not present in a computer systemSILICON GRAPHICS INC·Filed 1999·Granted Jan 15, 2002·7 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Martin M. Deneroff files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →