System and Method for Performing Memory Operations In A Computing System

Abstract

A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

What is claimed is: 
     
         1 . A method of performing memory operations in a computing system, comprising:
 transitioning a cache line associated with a memory location from a conventional coherency protocol to one of a plurality of extended coherency protocol states associated with an operating state of a processor;   performing an update to the cache line associated with the memory location in accordance with the operating state of the processor, the update to the cache line not being visible to other processors in the computing system; and   tracking access to a memory location by identifying the cache line with the extended coherency protocol state according to the update performed.   
     
     
         2 . The method of  claim 1 , wherein the conventional coherency protocol includes a MESI coherency protocol. 
     
     
         3 . The method of  claim 1 , wherein the plurality of extended coherency protocol states is associated with a Transaction operating state of the processor. 
     
     
         4 . The method of  claim 1 , wherein the plurality of extended coherency protocol states includes a Shared Transactional state characterized by the cache line having a copy of data that is the same as the corresponding contents of the memory and one or more other cache lines also in a Shared Transactional state. 
     
     
         5 . The method of  claim 4 , when the cache line is in the Shared Transactional state and in response to an eviction of an address from the cache line, further comprising:
 adding the evicted address to an Eviction List; and   setting one of two cache tag constituent elements.   
     
     
         6 . The method of  claim 1 , wherein the plurality of extended coherency protocol states include an Exclusive state characterized by the cache line having an exclusive copy of data that is the same as the corresponding contents of the memory, such that no other cache has a copy of said data. 
     
     
         7 . The method of  claim 6 , when the cache line is in the Exclusive state, further comprising writing to the cache line without performing a coherency transaction. 
     
     
         8 . The method of  claim 1 , wherein the plurality of extended coherency protocol states include an Exclusive Transactional state characterized by the cache line having an exclusive copy of data that is the same as the corresponding contents of the memory, such that no other cache has a copy of said data. 
     
     
         9 . The method of  claim 8 , when the cache line is in the Exclusive Transactional state and in response to an eviction of an address from the cache line, further comprising:
 adding the evicted address to a Writeback List; and   setting one of two cache tag constituent elements.   
     
     
         10 . The method of  claim 8 , further comprising writing to the cache line without performing a coherency transaction when the cache line is in the Exclusive Transactional state. 
     
     
         11 . The method of  claim 1 , wherein the plurality of extended coherency protocol states include a Dirty state characterized by the cache line having modified data that is different from the corresponding contents of the memory, and wherein no other cache has a copy of the modified data. 
     
     
         12 . The method of  claim 11 , further comprising writing to the cache line without performing a coherency transaction when the cache line is in the Exclusive Transactional state. 
     
     
         13 . The method of  claim 1 , wherein the plurality of extended coherency protocol states include a Dirty Transactional state characterized by the cache line having modified data that is different from the corresponding contents of the memory. 
     
     
         14 . The method of  claim 13 , when the cache line is in the Dirty Transactional state and in response to an eviction of an address from the cache line, further comprising:
 adding the evicted address and data to a Writeback List; and   setting one of two cache tag constituent elements.