Inventor · disambiguated record
Krste Asanovic
Also filed as: ASANOVIC KRSTE
24 granted patents·8 pending applications·195 citations·filing 1996–2025
92Inventor score
Technology areasG06F
Files withSIFIVE INC26MILLER STEVEN C2INT COMPUTER SCIENCE INST1MASSACHUSETTS INST TECHNOLOGY1SILICON GRAPHICS INC1
Top patents by PatentIndex Score
32 records- 0191US7287140B1System and technique for fine-grained computer memory protectionMASSACHUSETTS INST TECHNOLOGY·Filed 2004·Granted Oct 23, 2007·118 cites·45 claims
- 0280US11861365B2Macro-op fusionSIFIVE INC·Filed 2021·Granted Jan 2, 2024·1 cites·20 claims
- 0380US2025383877A1Fusion with destructive instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 0474US12487829B2Macro-op fusion for pipelined architecturesSIFIVE INC·Filed 2024·Granted Dec 2, 2025·0 cites·20 claims
- 0571US12417103B2Fusion with destructive instructionsSIFIVE INC·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 0670US10996952B2Macro-op fusionSIFIVE INC·Filed 2018·Granted May 4, 2021·1 cites·39 claims
- 0769US5805875AVector processing system with multi-operation, run-time configurable pipelinesINT COMPUTER SCIENCE INST·Filed 1996·Granted Sep 8, 1998·72 cites·9 claims
- 0867US2025173277A1Memory protection for gather-scatter operationsSIFIVE INC·Filed 2025·Application pending·0 cites
- 0966US11797308B2Fetch stage handling of indirect jumps in a processor pipelineSIFIVE INC·Filed 2022·Granted Oct 24, 2023·0 cites·20 claims
- 1064US7925839B1System and method for performing memory operations in a computing systemSILICON GRAPHICS INTERNAT·Filed 2008·Granted Apr 12, 2011·2 cites·13 claims
- 1163US12253959B2Memory protection for gather-scatter operationsSIFIVE INC·Filed 2021·Granted Mar 18, 2025·0 cites·15 claims
- 1263US11966290B2Checker cores for fault tolerant processingSIFIVE INC·Filed 2023·Granted Apr 23, 2024·0 cites·20 claims
- 1361US12468540B2Technologies for prediction-based register renamingSIFIVE INC·Filed 2021·Granted Nov 11, 2025·0 cites·12 claims
- 1461US12430132B2Technologies for interconnect address remapper with event recognition and register managementSIFIVE INC·Filed 2022·Granted Sep 30, 2025·0 cites·20 claims
- 1561US12086067B2Load-store pipeline selection for vectorsSIFIVE INC·Filed 2023·Granted Sep 10, 2024·0 cites·22 claims
- 1660US11687342B2Way predictor and enable logic for instruction tightly-coupled memory and instruction cacheSIFIVE INC·Filed 2019·Granted Jun 27, 2023·0 cites·20 claims
- 1758US11301251B2Fetch stage handling of indirect jumps in a processor pipelineSIFIVE INC·Filed 2020·Granted Apr 12, 2022·0 cites·20 claims
- 1858US11048515B2Way predictor and enable logic for instruction tightly-coupled memory and instruction cacheSIFIVE INC·Filed 2019·Granted Jun 29, 2021·0 cites·8 claims
- 1956US11556413B2Checker cores for fault tolerant processingSIFIVE INC·Filed 2020·Granted Jan 17, 2023·0 cites·27 claims
- 2054US12346268B2Address range encoding in system on a chip with securely partitioned memory spaceSIFIVE INC·Filed 2023·Granted Jul 1, 2025·0 cites·20 claims
- 2154US2024338320A1Page table entry caches with multiple tag lengthsSIFIVE INC·Filed 2024·Application pending·0 cites
- 2252US12437121B2Efficient processing of masked memory accessesSIFIVE INC·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 2352US12314191B2Memory protection for vector operationsSIFIVE INC·Filed 2021·Granted May 27, 2025·0 cites·23 claims
- 2452US2013080709A1System and Method for Performing Memory Operations In A Computing SystemMILLER STEVEN C·Filed 2012·Application pending·0 cites
- 2551US8321634B2System and method for performing memory operations in a computing systemMILLER STEVEN C·Filed 2011·Granted Nov 27, 2012·0 cites·22 claims
- 2651US2024020124A1Supporting Multiple Vector Lengths with Configurable Vector Register FileSIFIVE INC·Filed 2023·Application pending·0 cites
- 2750US7398359B1System and method for performing memory operations in a computing systemSILICON GRAPHICS INC·Filed 2004·Granted Jul 8, 2008·1 cites·20 claims
- 2850US2023367599A1Vector Gather with a Narrow DatapathSIFIVE INC·Filed 2023·Application pending·0 cites
- 2948US2023333861A1Configuring a component of a processor core based on an attribute of an operating system processSIFIVE INC·Filed 2023·Application pending·0 cites
- 3046US11429392B2Secure predictors for speculative executionSIFIVE INC·Filed 2019·Granted Aug 30, 2022·0 cites·28 claims
- 3140US2022292183A1Secure control flow predictionSIFIVE INC·Filed 2022·Application pending·0 cites
- 3236US11347507B2Secure control flow predictionSIFIVE INC·Filed 2019·Granted May 31, 2022·0 cites·58 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →