Scaling of Integrated Circuit Design Including High-Level Logic Components

Abstract

In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.

What is claimed is: 
     
         1 . A non-transitory computer-readable storage medium storing executable computer program instructions for estimating a trial PPA (power, performance, area) metric for an integrated circuit design evaluated at a trial design point, the instructions executable by a processor and causing the processor to perform a method comprising:
 receiving an integrated circuit design, the integrated circuit design comprising a logic portion and a memory portion, the logic portion represented by a count of logic gates;   estimating a trial PPA metric for the logic portion evaluated at the trial design point, comprising:
 accessing a reference PPA metric for an equivalent test component for the logic portion, the equivalent test component based on the count of logic gates for the logic portion and the reference PPA metric evaluated at a reference design point; 
 determining a logic scale factor for the logic portion, the logic scale factor based on: scaling from (a) the reference design point to (b) the trial design point, of the equivalent test component for the logic portion; and 
 applying the logic scale factor to the reference PPA metric to determine the trial PPA metric at the trial design point; 
   estimating a trial PPA metric for the memory portion evaluated at the trial design point; and   combining the trial PPA metric for the logic portion and the trial PPA metric for the memory portion to obtain a trial PPA metric for the integrated circuit design evaluated at the trial design point.   
     
     
         2 . The non-transitory computer-readable storage medium of  claim 1 , wherein the logic portion of the integrated circuit design is represented by the count of logic gates without specifying any actual logic components, and determining the logic scale factor does not depend on the actual logic components contained in the logic portion. 
     
     
         3 . The non-transitory computer-readable storage medium of  claim 1 , wherein the logic portion of the integrated circuit design is represented by the count of logic gates without any RTL representation of the logic portion, and determining the logic scale factor does not depend on any RTL representation of the logic portion. 
     
     
         4 . The non-transitory computer-readable storage medium of  claim 1 , wherein estimating the trial PPA metric for the logic portion occurs before synthesis of an RTL representation of the logic portion. 
     
     
         5 . The non-transitory computer-readable storage medium of  claim 1 , wherein estimating the trial PPA metric for the logic portion occurs at an early design stage before an actual logic design of the logic portion is available. 
     
     
         6 . The non-transitory computer-readable storage medium of  claim 1 , wherein the PPA metric includes at least one of: dynamic power, leakage power, operating frequency, and die area. 
     
     
         7 . The non-transitory computer-readable storage medium of  claim 1 , wherein the count of logic gates representing the logic portion is a count of a single type of logic gate. 
     
     
         8 . The non-transitory computer-readable storage medium of  claim 7 , wherein the single type of logic gate is either a NAND logic gate or a NOR logic gate. 
     
     
         9 . The non-transitory computer-readable storage medium of  claim 1 , wherein the count of logic gates representing the logic portion includes a count of NAND logic gates or a count of NOR logic gates. 
     
     
         10 . The non-transitory computer-readable storage medium of  claim 1 , wherein the equivalent test component to the logic portion is determined based on a type of logic gate used in the count of logic gates representing the logic portion. 
     
     
         11 . The non-transitory computer-readable storage medium of  claim 1  wherein the logic scale factor for the logic portion comprises a technology scale factor that accounts for differences in technology node and library. 
     
     
         12 . The non-transitory computer-readable storage medium of  claim 1  wherein the logic scale factor for the logic portion comprises a PVT scale factor that accounts for differences in PVT conditions. 
     
     
         13 . The non-transitory computer-readable storage medium of  claim 1 , wherein the memory portion is represented by a specified memory component, and estimating a trial PPA metric for the memory portion evaluated at the trial design point comprises:
 accessing a reference PPA metric for the memory component design evaluated at a reference design point;   determining a scale factor for the memory component, the scale factor based on: scaling from (a) the reference design point to (b) the trial design point, of an equivalent test component to the memory component; and   applying the scale factor to the reference PPA metric to determine the trial PPA metric for the memory portion at the trial design point.   
     
     
         14 . The non-transitory computer-readable storage medium of  claim 1  wherein:
 the integrated circuit design comprises a plurality of logic portions and a plurality of memory portions; 
 estimating a trial PPA metric for the logic portion evaluated at the trial design point comprises estimating a trial PPA metric for each of the logic portions evaluated at the trial design point; 
 estimating a trial PPA metric for the memory portion evaluated at the trial design point comprises estimating a trial PPA metric for each of the memory portions evaluated at the trial design point; and 
 combining the trial PPA metric for the logic portion and the trial PPA metric for the memory portion comprises combining the trial PPA metrics for all of the logic portions and the trial PPA metrics for all of the memory portions to obtain a trial PPA metric for the integrated circuit design evaluated at the trial design point. 
 
     
     
         15 . The non-transitory computer-readable storage medium of  claim 14 , wherein the integrated circuit design is a design for a system-on-chip (SoC). 
     
     
         16 . A non-transitory computer-readable storage medium storing executable computer program instructions for recommending a design point for an integrated circuit design, the instructions executable by a processor and causing the processor to perform a method comprising:
 receiving an integrated circuit design, the integrated circuit design comprising a logic portion and a memory portion, the logic portion represented by a count of logic gates;   receiving a target PPA metric for the integrated circuit design;   estimating trial PPA metrics for the integrated circuit design evaluated at a plurality of trial design points according to the computer program instructions of  claim 1 ; and   based on the estimated trial PPA metrics and the target PPA metric, recommending a trial design point for the integrated circuit design.   
     
     
         17 . The non-transitory computer-readable storage medium of  claim 16 , wherein the plurality of trial design points includes design points at different process foundries, different node geometries and/or different process variants; and recommending the trial design point comprises recommending from among the different process foundries, different node geometries and/or different process variants. 
     
     
         18 . The non-transitory computer-readable storage medium of  claim 16 , wherein the plurality of trial design points includes design points using different libraries, the different libraries include libraries from different library vendors and/or with different numbers of tracks; and recommending the trial design point comprises recommending from among the different library vendors and/or with different numbers of tracks. 
     
     
         19 . The non-transitory computer-readable storage medium of  claim 16 , wherein the method further comprises:
 receiving design constraints on the integrated circuit design, wherein recommending a trial design point is further based on meeting said design constraints.   
     
     
         20 . A non-transitory computer-readable storage medium storing executable computer program instructions for optimizing a design point for an integrated circuit design, the instructions executable by a processor and causing the processor to perform a method comprising:
 receiving an integrated circuit design, the integrated circuit design comprising a logic portion and a memory portion, the logic portion represented by a count of logic gates;   receiving a target PPA metric for the integrated circuit design;   estimating trial PPA metrics for the integrated circuit design evaluated at a plurality of trial design points according to the computer program instructions of  claim 1 ; and   iteratively optimizing the trial design point, based on the estimated trial PPA metrics and the target PPA metric.