Semiconductor device

Abstract

Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

1 . A semiconductor device, comprising:
 a substrate including first, second, and third logic cells, the second and third logic cells being spaced apart from each other in a first direction with the first logic cell interposed therebetween;   active patterns provided in each of the first to third logic cells to protrude from the substrate; and   gate structures crossing the active patterns,   wherein the active patterns are arranged in the first direction and extend in a second direction crossing the first direction, and   a first distance between a first adjacent pair of the active patterns, which include one from the first logic cell and other one from the second logic cell, that are most adjacent to each other in the first direction is different from a second distance between a second adjacent pair of the active patterns, which include one from the first logic cell and other one from the third logic cell, that are most adjacent to each other in the first direction.   
     
     
         2 . The semiconductor device of  claim 1 , wherein each of the first to third logic cells comprises first and second active regions having conductivity types different from each other,
 the active patterns constitute the first and second active regions of each of the first to third logic cells,   the active patterns in the first active region are provided to have a first pitch,   the active patterns in the second active region are provided to have a second pitch that is substantially the same as the first pitch, and   a difference between the first and second distances is substantially the same as the first pitch.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising a first device isolation layer provided in each of the first to third logic cells,
 wherein the first device isolation layer is provided between the first and second active regions of each of the first to third logic cells and in the substrate to extend in the second direction.   
     
     
         4 . The semiconductor device of  claim 3 , wherein a first width of the first device isolation layer measured in the first direction is larger than the first pitch. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the first and second logic cells share a first cell boundary that is positioned between the first and second logic cells to extend in the second direction,
 the first and third logic cells share a second cell boundary that is positioned between the first and third logic cells to extend in the second direction,   the first logic cell has an internal boundary that is equidistant from adjacent ones of the active patterns spaced apart from each other with the first device isolation layer interposed therebetween, and   when viewed in a plan view, a first height from the internal boundary to the first cell boundary is different from a second height from the second cell boundary to the internal boundary.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the first cell boundary is equidistant from the first adjacent pair of the active patterns defining the first distance, and
 the second cell boundary is equidistant from the second adjacent pair of the active patterns defining the second distance.   
     
     
         7 . The semiconductor device of  claim 6 , wherein a difference between the first and second heights is half the first pitch. 
     
     
         8 . The semiconductor device of  claim 5 , further comprising:
 an upper second device isolation layer provided in the substrate and between adjacent ones of the active patterns with one in the first logic cell and other one in the second logic cell; and   a lower second device isolation layer provided in the substrate and between adjacent ones of the active patterns with one in the first logic cell and other one in the third logic cell,   wherein the upper and lower second device isolation layers extend in the second direction, and   when measured in the first direction, a second width of the upper second device isolation layer is different from a third width of the lower second device isolation layer.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first cell boundary is defined as a center line of the upper second device isolation layer, and
 the second cell boundary is defined as a center line of the lower second device isolation layer.   
     
     
         10 . The semiconductor device of  claim 8 , wherein each of the active regions of the first and second logic cells adjacent to each other is the first active region, and
 each of the active regions of the first and third logic cells adjacent to each other is the second active region.   
     
     
         11 . The semiconductor device of  claim 8 , wherein, when the first height is greater than the second height, the first distance is greater than the second distance and the second width is greater than the third width, and
 when the second height is greater than the first height, the first distance is smaller than the second distance and the second width is smaller than the third width.   
     
     
         12 . The semiconductor device of  claim 8 , further comprising:
 source/drain regions provided on the active patterns and at both sides of the gate structures;   source/drain contacts connected to at least one of the source/drain regions;   a first common conductive line extending along the first cell boundary and in the second direction, the first common conductive line being overlapped with the upper second device isolation layer; and   a second common conductive line extending along the second cell boundary and in the second direction, the second common conductive line being overlapped with the lower second device isolation layer,   wherein at least one of the source/drain contacts is connected to the first common conductive line, and   at least one other of the source/drain contacts is connected to the second common conductive line.   
     
     
         13 . The semiconductor device of  claim 12 , wherein, when measured in the first direction, the first common conductive line has a fourth width and the second common conductive line has a fifth width, the fourth width is different from the fifth width. 
     
     
         14 . The semiconductor device of  claim 13 , wherein, when the first height is greater than the second height, the fourth width is greater than the fifth width, and
 when the second height is greater than the first height, the fourth width is smaller than the fifth width.   
     
     
         15 . The semiconductor device of  claim 8 , further comprising a third device isolation layer, which is provided on the substrate and at both sides of the active patterns and is formed to expose upper portions of the active patterns,
 wherein the third device isolation layer is thinner than the first device isolation layer.   
     
     
         16 . A semiconductor device, comprising:
 a substrate including a plurality of logic cells arranged in a first direction, each of the plurality of logic cells comprising first and second regions that are spaced apart from each other in the first direction;   active patterns provided in each of the first and second regions and arranged in the first direction, the active patterns protruding from the substrate and extending in a second direction crossing the first direction; and   gate structures arranged in the second direction to extend in the first direction and cross at least one of the active patterns,   wherein a conductivity type of the active patterns of the first region is different from that of the active patterns of the second region, and   wherein each of the plurality of logic cells comprises:   first and second cell boundaries, each of which is shared by adjacent ones of the logic cells facing each other in the first direction; and   an internal boundary interposed between the first and second regions and being equidistant from an adjacent pair of the active patterns, which include one from the first region and other one from the second region, that are most adjacent to each other in the first direction,   a first height from the internal boundary to the first cell boundary is greater than a second height from the second cell boundary to the internal boundary.   
     
     
         17 . The semiconductor device of  claim 16 , wherein a pitch of the active patterns of the first region is substantially the same as that of the active patterns of the second region, and
 the first height is greater by half the pitch than the second height.   
     
     
         18 . The semiconductor device of  claim 17 , wherein, when viewed in a plan view, each of the plurality of logic cells has a cell height that is defined as a distance between the first and second cell boundaries, and
 the cell heights of the plurality of logic cells are substantially the same.   
     
     
         19 . The semiconductor device of  claim 17 , wherein the first cell boundary is defined as a center line between the active patterns that are most adjacent to each other with the first cell boundary interposed therebetween, and
 the second cell boundary is defined as a center line between the active patterns that are most adjacent to each other with the second cell boundary interposed therebetween.   
     
     
         20 . The semiconductor device of  claim 19 , wherein a distance between the active patterns defining the first cell boundary is greater by the pitch than a distance between the active patterns defining the second cell boundary. 
     
     
         21 .- 26 . (canceled)