3d nand array with divided string architecture

Abstract

A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a plurality of charge storing devices connected to form a cell string; and   one or more internal select gates connected between selected charge storing devices in the cell string, wherein the one or more internal select gates divide the cell string into two or more segments of charge storing devices, and wherein selectively enabling and disabling the one or more internal select gates during programming isolates one or more selected segments to reduce program-disturb to remaining segments.   
     
     
         2 . The apparatus of  claim 1 , wherein the cell string comprises a channel and at least one internal select gate blocks current flow through the channel when the at least one internal select gate is disabled. 
     
     
         3 . The apparatus of  claim 1 , wherein the one or more internal select gates are charge storing devices. 
     
     
         4 . The apparatus of  claim 1 , wherein the one or more internal select gates are non-charge storing devices. 
     
     
         5 . The apparatus of  claim 1 , wherein the plurality of charge storing devices and the one or more internal select gates form a linear cell string. 
     
     
         6 . The apparatus of  claim 1 , wherein the plurality of charge storing devices and the one or more internal select gates form a non-linear cell string. 
     
     
         7 . A 3D memory array, comprising:
 a plurality of cell strings, wherein each cell string has a plurality of charge storing devices; and   one or more internal select gates connected between selected charge storing devices in the cell strings, wherein the one or more internal select gates divide each cell string into two or more segments of charge storing devices, and wherein selectively enabling and disabling the one or more internal select gates during programming isolates one or more selected segments to reduce program-disturb to remaining segments.   
     
     
         8 . The array of  claim 7 , wherein at least two cell strings have a common internal select gate. 
     
     
         9 . The array of  claim 7 , wherein the one or more internal select gates are charge storing devices. 
     
     
         10 . The array of  claim 7 , wherein the one or more internal select gates are non-charge storing devices. 
     
     
         11 . The apparatus of  claim 7 , wherein the cell strings are linear cell strings. 
     
     
         12 . The apparatus of  claim 7 , wherein the cell strings are non-linear cell strings. 
     
     
         13 . A method for programming memory cells of a cell string having internal select gates that divides the cell string into segments, comprising:
 identifying a segment of the cell string containing a memory cell to be programmed;   applying a first voltage to a source selected gate of the cell string;   applying a second voltage to a drain select gate and the internal select gates of the cell string;   applying a third voltage to a bit line of the cell string;   ramping up a fourth voltage to a selected word line of the segment; and   ramping up a fifth voltage to unselected word lines of the segment.   
     
     
         14 . The method of  claim 13 , wherein the first voltage is zero volts. 
     
     
         15 . The method of  claim 13 , wherein the second voltage is VDD. 
     
     
         16 . The method of  claim 13 , wherein the fourth voltage is 20 volts. 
     
     
         17 . The method of  claim 13 , wherein the fifth voltage is in the range of 8 to 10 volts. 
     
     
         18 . The method of  claim 13 , disabling a first internal select gate after ramping up voltages to the selected and unselected word lines to prevent program-disturb to other segments. 
     
     
         19 . The method of  claim 18 , further comprising
 identifying a second segment of the cell string containing a second memory cell to be programmed;   applying a sixth voltage to the bit line of the cell string;   ramping up an eighth voltage to a selected word line of the second segment; and   ramping up a ninth voltage to unselected word lines of the second segment.   
     
     
         20 . The method of  claim 19 , disabling a second internal select gate after ramping up voltages to the selected and unselected word lines of the second segment to prevent program-disturb to other segments, and wherein the memory cell and the second memory cell are programmed substantially simultaneously.